8305AGLF Integrated Device Technology (Idt), 8305AGLF Datasheet - Page 2

• Manufacturer Part Number: 8305AGLF
• Description: Clock Driver 2-IN LVCMOS/LVTTL 16-Pin TSSOP Tube
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 8305AGLF

• Package: 16TSSOP
• Configuration: 1 x 2:1
• Input Signal Type: HCSL|LVCMOS|LVDS|LVHSTL|LVPECL|LVTTL|SSTL
• Maximum Output Frequency: 350 MHz
• Operating Supply Voltage: 3.3 V

Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
Symbol
C
R
R
C
R
10, 12, 14, 16
ICS8305
LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
IN
PULLUP
PULLDOWN
PD
OUT
Number
1, 9, 13
11, 15
2
3
4
5
6
7
8
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Power Dissipation Capacitance
(per output)
Output Impedance
Q3, Q2, Q1, Q0
LVCMOS_CLK
CLK_SEL
CLK_EN
Name
nCLK
V
GND
CLK
V
OE
DDO
DD
Output
Power
Power
Power
Input
Input
Input
Input
Input
Input
Type
Pulldown
Pulldown
Pulldown
Pullup/
Pullup
Pullup
Pullup
Test Conditions
Description
Power supply ground
Output enable. When LOW, outputs are in HIGH impedance state.
When HIGH, outputs are active. LVCMOS/LVTTL interface levels.
Power supply pin.
Synchronizing clock enable. When LOW, the output clocks are disabled.
When HIGH, output clocks are enabled. LVCMOS/LVTTL interface levels.
Non-inverting differential clock input.
Inverting differential clock input. VDD/2 default when left floating.
Clock select input. When HIGH, selects CLK, nCLK inputs. When LOW,
selects LVCMOS_CLK input. LVCMOS/LVTTL interface levels.
Single-ended clock input. LVCMOS/LVTTL interface levels.
Single-ended clock outputs. 7
LVCMOS/LVTTL interface levels.
Output supply pins.
2
Minimum
Ω
output impedance.
ICS8305AG REV. C FEBRUARY 22, 2008
Typical
51
51
11
7
4
Maximum
Units
k
k
pF
pF
Ω
Ω
Ω