74HC74D NXP Semiconductors, 74HC74D Datasheet - Page 2

• Manufacturer Part Number: 74HC74D
• Description: Flip Flop D-Type Pos-Edge 2-Element 14-Pin SO Bulk
• Manufacturer: NXP Semiconductors

Specifications of 74HC74D

• Package: 14SO
• Logic Function: D-Type
• Logic Family: HC
• Number Of Element Outputs: 1
• Number Of Elements Per Chip: 2
• Input Signal Type: Single-Ended
• Output Signal Type: Differential
• Set/reset: Set/Reset
• Typical Operating Supply Voltage: 5 V
• Operating Temperature: -40 to 125 °C

Philips Semiconductors
FEATURES
QUICK REFERENCE DATA
GND = 0 V; T
Notes
1. C
2. For 74HC74 the condition is V
2003 Jul 10
t
f
C
C
PHL
max
SYMBOL
Wide supply voltage range from 2.0 to 6.0 V
Symmetrical output impedance
High noise immunity
Low power dissipation
Balanced propagation delays
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
I
PD
Dual D-type flip-flop with set and reset;
positive-edge trigger
P
f
f
C
V
N = total load switching outputs;
For 74HCT74 the condition is V
i
o
/t
(C
D
CC
PD
= input frequency in MHz;
L
PLH
= output frequency in MHz;
= output load capacitance in pF;
= C
L
is used to determine the dynamic power dissipation (P
= supply voltage in Volts;
PD
V
CC
amb
propagation delay
maximum clock frequency
input capacitance
power dissipation capacitance per flip-flop
2
V
nCP to nQ, nQ
nSD to nQ, nQ
nRD to nQ, nQ
CC
= 25 C; t
f
o
2
) = sum of the outputs.
f
i
N + (C
r
= t
PARAMETER
f
= 6 ns
I
L
= GND to V
I
= GND to V
V
CC
2
f
o
CC
) where:
CC
.
1.5 V.
2
C
notes 1 and 2
GENERAL DESCRIPTION
The 74HC/HCT74 is a high-speed Si-gate CMOS device
and is pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT74 are dual positive-edge triggered, D-type
flip-flops with individual data (D) inputs, clock (CP) inputs,
set (SD) and reset (RD) inputs; also complementary
Q and Q outputs.
The set and reset are asynchronous active LOW inputs
and operate independently of the clock input. Information
on the data input is transferred to the Q output on the
LOW-to-HIGH transition of the clock pulse. The D inputs
must be stable one set-up time prior to the LOW-to-HIGH
clock transition for predictable operation.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
L
D
= 15 pF; V
in W).
CONDITIONS
CC
= 5 V
74HC74; 74HCT74
14
15
16
76
3.5
24
HC
TYPICAL
Product specification
15
18
18
59
3.5
29
HCT
ns
ns
ns
MHz
pF
pF
UNIT