74LVC74APW-T NXP Semiconductors, 74LVC74APW-T Datasheet - Page 14
74LVC74APW-T
Manufacturer Part Number
74LVC74APW-T
Description
Flip Flop D-Type Pos-Edge 2-Element 14-Pin TSSOP T/R
Manufacturer
NXP Semiconductors
Datasheet
1.74LVC74AD118.pdf
(16 pages)
Specifications of 74LVC74APW-T
Package
14TSSOP
Logic Function
D-Type
Logic Family
LVC
Number Of Element Outputs
1
Number Of Elements Per Chip
2
Input Signal Type
Single-Ended
Output Signal Type
Differential
Set/reset
Set/Reset
Typical Operating Supply Voltage
1.8|2.5|3.3 V
Operating Temperature
-40 to 125 °C
NXP Semiconductors
13. Abbreviations
Table 10.
14. Revision history
Table 11.
74LVC74A_6
Product data sheet
Acronym
CDM
DUT
ESD
HBM
TTL
Document ID
74LVC74A_6
74LVC74A_5
74LVC74A_4
74LVC74A_3
74LVC74A_2
74LVC74A_1
Modifications:
Abbreviations
Revision history
Description
Charged Device Model
Device Under Test
ElectroStatic Discharge
Human Body Model
Transistor-Transistor Logic
Release date
20070604
20070525
20030526
20020618
19980617
19980617
•
Change of hold time in
Data sheet status
Product data sheet
Product data sheet
Product specification
Product specification
Product specification
Product specification
Rev. 06 — 4 June 2007
Dual D-type flip-flop with set and reset; positive-edge trigger
Table 8 “Dynamic
characteristics”. Minimum values changed to 1.0 ns.
Change notice
-
-
-
-
-
-
Supersedes
74LVC74A_5
74LVC74A_4
74LVC74A_3
74LVC74A_2
74LVC74A_1
-
74LVC74A
© NXP B.V. 2007. All rights reserved.
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