MT47H64M8CF-25E IT:G Micron Technology Inc, MT47H64M8CF-25E IT:G Datasheet - Page 109

• Manufacturer Part Number: MT47H64M8CF-25E IT:G
• Description: 64MX8 DDR2 SDRAM PLASTIC IND TEMP FBGA 1.8V
• Manufacturer: Micron Technology Inc

Figure 64: Data Input Timing
PRECHARGE
PDF: 09005aef8440dbbc
512mbddr2_ait_aat.pdf – Rev. C 7/11 EN
Notes:
DQS#
Precharge can be initiated by either a manual PRECHARGE command or by an autopre-
charge in conjunction with either a READ or WRITE command. Precharge will deacti-
vate the open row in a particular bank or the open row in all banks. The PRECHARGE
operation is shown in the previous READ and WRITE operation sections.
During a manual PRECHARGE command, the A10 input determines whether one or all
banks are to be precharged. In the case where only one bank is to be precharged, bank
address inputs determine the bank to be precharged. When all banks are to be pre-
charged, the bank address inputs are treated as “Don’t Care.”
Once a bank has been precharged, it is in the idle state and must be activated prior to
any READ or WRITE commands being issued to that bank. When a single-bank PRE-
CHARGE command is issued,
mand is issued,
DQS
CK#
DM
DQ
CK
1.
2.
3. Subsequent rising DQS signals must align to the clock within
4. WRITE command issued at T0.
5. For x16, LDQS controls the lower byte and UDQS controls the upper byte.
6. WRITE command with WL = 2 (CL = 3, AL = 0) issued at T0.
t
t
DSH (MIN) generally occurs during
DSS (MIN) generally occurs during
T0
Micron Confidential and Proprietary
WL - t DQSS (NOM)
t
RPA timing applies, regardless of the number of banks opened.
T1
T1n
t WPRE
109
t
512Mb: x8, x16 Automotive DDR2 SDRAM
T2
DI
RP timing applies. When the PRECHARGE (ALL) com-
t DSH 1
T2n
t DQSL
t DSS 2
t
t
DQSS (MAX).
DQSS (MIN).
Micron Technology, Inc. reserves the right to change products or specifications without notice.
Transitioning Data
T3
3
t DQSH
t DSH 1
T3n
t WPST
t DSS 2
T4
Don’t Care
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t
DQSS.
PRECHARGE