MT47H64M8CF-25E IT:G Micron Technology Inc, MT47H64M8CF-25E IT:G Datasheet - Page 111
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MT47H64M8CF-25E IT:G
Manufacturer Part Number
MT47H64M8CF-25E IT:G
Description
64MX8 DDR2 SDRAM PLASTIC IND TEMP FBGA 1.8V
Manufacturer
Micron Technology Inc
- Current page: 111 of 129
- Download datasheet (3Mb)
SELF REFRESH
PDF: 09005aef8440dbbc
512mbddr2_ait_aat.pdf – Rev. C 7/11 EN
The SELF REFRESH command is initiated when CKE is LOW. The differential clock
should remain stable and meet
fresh mode. The procedure for exiting self refresh requires a sequence of commands.
First, the differential clock must be stable and meet
prior to CKE going back to HIGH. Once CKE is HIGH (
with three clock registrations), the DDR2 SDRAM must have NOP or DESELECT com-
mands issued for
ments is used to apply NOP or DESELECT commands for 200 clock cycles before apply-
ing any other command.
Micron Confidential and Proprietary
t
XSNR. A simple algorithm for meeting both refresh and DLL require-
111
512Mb: x8, x16 Automotive DDR2 SDRAM
t
CKE specifications at least 1 ×
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
CK specifications at least 1 ×
t
CKE [MIN] has been satisfied
2010 Micron Technology, Inc. All rights reserved.
t
CK after entering self re-
SELF REFRESH
t
CK
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