MT48LC16M16A2P-75 L:D TR Micron Technology Inc, MT48LC16M16A2P-75 L:D TR Datasheet - Page 42
![DRAM Chip SDRAM 256M-Bit 16Mx16 3.3V 54-Pin TSOP-II T/R](/photos/7/22/72261/557-54-tsop_sml.jpg)
MT48LC16M16A2P-75 L:D TR
Manufacturer Part Number
MT48LC16M16A2P-75 L:D TR
Description
DRAM Chip SDRAM 256M-Bit 16Mx16 3.3V 54-Pin TSOP-II T/R
Manufacturer
Micron Technology Inc
Type
SDRAMr
Specifications of MT48LC16M16A2P-75 L:D TR
Package
54TSOP-II
Density
256 Mb
Address Bus Width
15 Bit
Operating Supply Voltage
3.3 V
Maximum Clock Rate
133 MHz
Maximum Random Access Time
6|5.4 ns
Operating Temperature
0 to 70 °C
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
256M (16Mx16)
Speed
133MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Package / Case
54-TSOP II
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
557-1191-2
Table 19: Truth Table – CKE
Notes 1–4 apply to all parameters and conditions
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. N 1/10 EN
Current State
Power-down
Self refresh
Clock suspend
Power-down
Self refresh
Clock suspend
All banks idle
All banks idle
Reading or writing
Notes:
CKE
H
H
L
L
n-1
1. CKE
2. Current state is the state of the SDRAM immediately prior to clock edge n.
3. COMMAND
4. All states and sequences not shown are illegal or reserved.
5. Exiting power-down at clock edge n will put the device in the all banks idle state in time
6. Exiting self refresh at clock edge n will put the device in the all banks idle state after
7. After exiting clock suspend at clock edge n, the device will resume operation and recog-
ous clock edge.
MAND
for clock edge n + 1 (provided that
t
occurring during the
during the
nize the next command at clock edge n + 1.
XSR is met. COMMAND INHIBIT or NOP commands should be issued on any clock edges
CKE
H
H
L
L
n
n
is the logic state of CKE at clock edge n; CKE
n
.
t
n
XSR period.
is the command registered at clock edge n, and ACTION
COMMAND INHIBIT or NOP
COMMAND INHIBIT or NOP
COMMAND INHIBIT or NOP
See Table 18 (page 40).
t
XSR period. A minimum of two NOP commands must be provided
AUTO REFRESH
Command
42
VALID
X
X
X
X
n
t
CKS is met).
Micron Technology, Inc. reserves the right to change products or specifications without notice.
256Mb: x4, x8, x16 SDRAM
n-1
Maintain clock suspend
was the state of CKE at the previ-
Maintain power-down
Maintain self refresh
Clock suspend entry
Power-down entry
Exit clock suspend
Exit power-down
Self refresh entry
Exit self refresh
Action
© 1999 Micron Technology, Inc. All rights reserved.
n
n
is a result of COM-
Truth Tables
Notes
5
6
7