MT48LC16M16A2P-75 L:D TR Micron Technology Inc, MT48LC16M16A2P-75 L:D TR Datasheet - Page 59
![DRAM Chip SDRAM 256M-Bit 16Mx16 3.3V 54-Pin TSOP-II T/R](/photos/7/22/72261/557-54-tsop_sml.jpg)
MT48LC16M16A2P-75 L:D TR
Manufacturer Part Number
MT48LC16M16A2P-75 L:D TR
Description
DRAM Chip SDRAM 256M-Bit 16Mx16 3.3V 54-Pin TSOP-II T/R
Manufacturer
Micron Technology Inc
Type
SDRAMr
Specifications of MT48LC16M16A2P-75 L:D TR
Package
54TSOP-II
Density
256 Mb
Address Bus Width
15 Bit
Operating Supply Voltage
3.3 V
Maximum Clock Rate
133 MHz
Maximum Random Access Time
6|5.4 ns
Operating Temperature
0 to 70 °C
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
256M (16Mx16)
Speed
133MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Package / Case
54-TSOP II
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
557-1191-2
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Figure 28: READ Continuous Page Burst
Command
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. N 1/10 EN
BA0, BA1
Address
DQM
CKE
A10
CLK
DQ
t CMS
t CKS
t AS
t AS
t AS
ACTIVE
Row
Row
Bank
T0
t CKH
t CMH
t AH
t AH
t AH
t RCD
t CL
T1
Note:
NOP
t CH
t CMS
1. For this example, CL = 2.
t CK
Column m
Bank
T2
READ
t CMH
CAS latency
T3
NOP
t LZ
t AC
T4
NOP
D
OUT
t OH
t AC
59
All locations within same row
T5
Full-page burst does not self-terminate.
D
NOP
Can use BURST TERMINATE command.
OUT
t OH
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t AC
Full page completed
T6
NOP
D
OUT
t OH
t AC
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256Mb: x4, x8, x16 SDRAM
)
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)
Tn + 1
NOP
D
OUT
t OH
t AC
© 1999 Micron Technology, Inc. All rights reserved.
BURST TERM
Tn + 2
READ Operation
D
OUT
t OH
t AC
Tn + 3
NOP
D
OUT
t OH
t HZ
Don’t Care
Undefined
Tn + 4
NOP
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