MT48LC4M16A2P-75 L:G Micron Technology Inc, MT48LC4M16A2P-75 L:G Datasheet - Page 63

DRAM Chip SDRAM 64M-Bit 4Mx16 3.3V 54-Pin TSOP-II Tray

MT48LC4M16A2P-75 L:G

Manufacturer Part Number
MT48LC4M16A2P-75 L:G
Description
DRAM Chip SDRAM 64M-Bit 4Mx16 3.3V 54-Pin TSOP-II Tray
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet

Specifications of MT48LC4M16A2P-75 L:G

Package
54TSOP-II
Density
64 Mb
Address Bus Width
14 Bit
Operating Supply Voltage
3.3 V
Maximum Clock Rate
133 MHz
Maximum Random Access Time
6|5.4 ns
Operating Temperature
0 to 70 °C
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
64M (4M x 16)
Speed
133MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Package / Case
54-TSOP II
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Figure 46:
PDF: 09005aef80725c0b/Source: 09005aef806fc13c
64MSDRAM_2.fm - Rev. N 12/08 EN
DQML, DQMH
COMMAND
A0-A9, A11
BA0, BA1
DQM /
CKE
A10
CLK
DQ
t CMS t CMH
t CKS
READ – DQM Operation
t AS
t AS
t AS
ACTIVE
T0
ROW
ROW
BANK
t CKH
Notes:
t AH
t AH
t AH
t RCD
t CK
1. For this example, BL = 4, and CL = 2.
2. x16: A8, A9 and A11 = “Don’t Care”
T1
NOP
x8: A9 and A11 = “Don’t Care”
x4: A11 = “Don’t Care”
DISABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
t CMS
t CL
COLUMN m 2
T2
READ
BANK
t CMH
t CH
CAS Latency
T3
NOP
t
LZ
t AC
63
T4
NOP
t OH
D
t HZ
OUT
m
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T5
NOP
t
LZ
t AC
T6
NOP
64Mb: x4, x8, x16 SDRAM
D
t AC
t OH
OUT
m + 2
©2000 Micron Technology, Inc. All rights reserved.
T7
NOP
Timing Diagrams
D
OUT
t OH
t HZ
m + 3
T8
NOP
DON’T CARE
UNDEFINED

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