MT48LC64M8A2TG-75 IT:C Micron Technology Inc, MT48LC64M8A2TG-75 IT:C Datasheet - Page 14

DRAM Chip SDRAM 512M-Bit 64Mx8 3.3V 54-Pin TSOP-II Tray

MT48LC64M8A2TG-75 IT:C

Manufacturer Part Number
MT48LC64M8A2TG-75 IT:C
Description
DRAM Chip SDRAM 512M-Bit 64Mx8 3.3V 54-Pin TSOP-II Tray
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet

Specifications of MT48LC64M8A2TG-75 IT:C

Package
54TSOP-II
Density
512 Mb
Address Bus Width
15 Bit
Operating Supply Voltage
3.3 V
Maximum Clock Rate
133 MHz
Maximum Random Access Time
6|5.4 ns
Operating Temperature
-40 to 85 °C
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
512M (64M x 8)
Speed
133MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Package / Case
54-TSOP II
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Figure 5:
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
M8
0
Mode Register Definition
M9
0
1
Notes:
M7
0
Programmed burst length
Single location access
Write Burst Mode
Defined
M6-M0
1. Should program M12, M11, M10 = “0, 0, 0” to ensure compatibility with future devices.
12
A12
Reserved
M6
11
A11
0
0
0
0
1
1
1
1
Operating Mode
Standard operation
All other states reserved
M5
1
0
0
1
1
0
0
1
1
10
A10
M4
0
1
0
1
0
1
0
1
WB
9
A9
Op Mode
CAS Latency
8
A8
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
2
3
7
A7
CAS Latency
6
A6
14
5
A5
4
A4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
M3
BT
0
1
3
A3
M2
0
0
0
0
1
1
1
1
Burst Length
2
A2
M1
0
0
1
1
0
0
1
1
M0
1
0
1
0
1
0
1
0
1
A1
512Mb: x4, x8, x16 SDRAM
0
A0
Full Page
Reserved
Reserved
Reserved
M3 = 0
Burst Type
Interleaved
Sequential
1
2
4
8
Mode Register (Mx)
Address Bus
Burst Length
©2000 Micron Technology, Inc. All rights reserved.
Register Definition
Reserved
Reserved
Reserved
Reserved
M3 = 1
1
2
4
8

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