723643L15PF Integrated Device Technology (Idt), 723643L15PF Datasheet

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723643L15PF

Manufacturer Part Number
723643L15PF
Description
FIFO Mem Sync Dual Depth/Width Bi-Dir 1K x 36 128-Pin TQFP
Manufacturer
Integrated Device Technology (Idt)
Datasheet
1.IDT723623L15PF8.pdf (28 pages)

Specifications of 723643L15PF

Package
128TQFP
Configuration
Dual
Bus Directional
Bi-Directional
Density
36 Kb
Organization
1Kx36
Data Bus Width
36 Bit
Timing Type
Synchronous
Expansion Type
Depth|Width
Typical Operating Supply Voltage
5 V
Operating Temperature
0 to 70 °C
©
FEATURES:
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
COMMERCIAL TEMPERATURE RANGE
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc.
FUNCTIONAL BLOCK DIAGRAM
Memory storage capacity:
Clocked FIFO buffering data from Port A to Port B
Clock frequencies up to 83 MHz (8 ns access time)
IDT Standard timing (using EF and FF) or First Word Fall
Through Timing (using OR and IR flag functions)
Programmable Almost-Empty and Almost-Full flags; each has
three default offsets (8, 16 and 64)
Serial or parallel programming of partial flags
Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits
(byte)
Big- or Little-Endian format for word and byte bus sizes
2009 Integrated Device Technology, Inc.
FS1/SEN
FS0/SD
MBF2
A
CLKA
W/RA
RS1
RS2
IDT723623
IDT723633
IDT723643
FF/IR
PRS
MBA
CSA
ENA
SPM
0
-A
AF
35
Control
Port-A
FIFO1
Mail1,
Mail2,
Reset
Logic
Logic
–
–
–
36
36
256 x 36
512 x 36
1,024 x 36
All rights reserved. Product specifications subject to change without notice.
10
CMOS BUS-MATCHING SyncFIFO
256 x 36, 512 x 36, 1,024 x 36
Programmable Flag
Offset Registers
36
Pointer
Write
Status Flag
1,024 x 36
RAM ARRAY
256 x 36
512 x 36
Register
Register
Mail 1
Logic
Mail 2
1
Pointer
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
DESCRIPTION:
CMOS unidirectional Synchronous (clocked) FIFO memories which support
Read
Timing
Mode
Reset clears data and configures FIFO, Partial Reset clears data
but retains configuration settings
Mailbox bypass registers for each FIFO
Free-running CLKA and CLKB may be asynchronous or
coincident (simultaneous reading and writing of data on a single
clock edge is permitted)
Easily expandable in width and depth
Auto power down minimizes power dissipation
Available in a space-saving 128-pin Thin Quad Flatpack (TQFP)
Industrial temperature range (–40° ° ° ° ° C to +85° ° ° ° ° C) is available
Green parts available, see ordering information
36
The IDT723623/723633/723643 are monolithic, high-speed, low-power,
TM
FEBRUARY 2009
36
36
Control
Port-B
Logic
IDT723623
IDT723633
IDT723643
3269 drw01
DSC-3269/4
B
EF/OR
AE
MBF1
FWFT
CLKB
CSB
W/RB
ENB
MBB
BE
BM
SIZE
0
-B
35

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723643L15PF Summary of contents

Page 1

FEATURES: • • • • • Memory storage capacity: IDT723623 – 256 x 36 IDT723633 – 512 x 36 IDT723643 – 1,024 x 36 • • • • • Clocked FIFO buffering data from Port A to Port B • ...

Page 2

IDT723623/723633/723643 BUS-MATCHING SyncFIFO™ 256 x 36, 512 x 36, 1,024 x 36 DESCRIPTION (CONTINUED) clock frequencies MHz and have read access times as fast as 8 ns. The 256/512/1,024 x 36 dual-port SRAM FIFO buffers data from ...

Page 3

IDT723623/723633/723643 BUS-MATCHING SyncFIFO™ 256 x 36, 512 x 36, 1,024 useful since it permits flushing of the FIFO memory without changing any configuration settings. These devices have two modes of operation: In the IDT Standard mode, the ...

Page 4

IDT723623/723633/723643 BUS-MATCHING SyncFIFO™ 256 x 36, 512 x 36, 1,024 x 36 PIN DESCRIPTIONS Symbol Name I/O A0-A35 Port A Data I/O 36-bit bidirectional data port for side A. AE Almost-Empty O Programmable Almost-Empty flag synchronized to CLKB ...

Page 5

IDT723623/723633/723643 BUS-MATCHING SyncFIFO™ 256 x 36, 512 x 36, 1,024 x 36 PIN DESCRIPTIONS (CONTINUED) Symbol Name I/O MBF2 MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the mail2 register. Writes to the mail2 ...

Page 6

IDT723623/723633/723643 BUS-MATCHING SyncFIFO™ 256 x 36, 512 x 36, 1,024 x 36 ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE RANGE (Unless otherwise noted) Symbol V Supply Voltage Range Input Voltage Range I ( (2) V Output Voltage ...

Page 7

IDT723623/723633/723643 BUS-MATCHING SyncFIFO™ 256 x 36, 512 x 36, 1,024 x 36 DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION The I current for the graph in Figure 1 was taken while simultaneously reading and writing a FIFO on the IDT723623/723633/723643 ...

Page 8

IDT723623/723633/723643 BUS-MATCHING SyncFIFO™ 256 x 36, 512 x 36, 1,024 x 36 TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE (Commercial 5.0V ± 10 0°C to +70° Symbol Parameter f ...

Page 9

IDT723623/723633/723643 BUS-MATCHING SyncFIFO™ 256 x 36, 512 x 36, 1,024 x 36 SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE (Commercial 5.0V ± 10 0°C to +70°C) CC ...

Page 10

IDT723623/723633/723643 BUS-MATCHING SyncFIFO™ 256 x 36, 512 x 36, 1,024 x 36 SIGNAL DESCRIPTION RESET (RS1/RS2) After power up, a Reset operation must be performed by providing a LOW pulse to RS1 and RS2 simultaneously. Afterwards, the FIFO memory of ...

Page 11

IDT723623/723633/723643 BUS-MATCHING SyncFIFO™ 256 x 36, 512 x 36, 1,024 x 36 TABLE 1 — FLAG PROGRAMMING SPM FS1/SEN FSO/ NOTE register ...

Page 12

IDT723623/723633/723643 BUS-MATCHING SyncFIFO™ 256 x 36, 512 x 36, 1,024 x 36 can be programmed from 1 to 508 (IDT723623 1,020 (IDT723633 2,044 (IDT723643). When the option to program the offset registers serially is chosen, ...

Page 13

IDT723623/723633/723643 BUS-MATCHING SyncFIFO™ 256 x 36, 512 x 36, 1,024 x 36 cycles of the Empty Flag synchronizing clock. Therefore, an Empty Flag is LOW if a word in memory is the next data to be sent to the FlFO ...

Page 14

IDT723623/723633/723643 BUS-MATCHING SyncFIFO™ 256 x 36, 512 x 36, 1,024 x 36 HIGH. For a 36-bit bus size, 36 bits of mailbox data are placed on B0-B35. For an 18-bit bus size, 18 bits of mailbox data are placed on ...

Page 15

IDT723623/723633/723643 BUS-MATCHING SyncFIFO™ 256 x 36, 512 x 36, 1,024 x 36 BYTE ORDER ON PORT SIZE BYTE ORDER ON PORT SIZE SIZE ...

Page 16

IDT723623/723633/723643 BUS-MATCHING SyncFIFO™ 256 x 36, 512 x 36, 1,024 x 36 CLKA CLKB t RSTS (3) RS1/RS2 BE/FWFT SPM FS1,FS0 FF/IR EF/OR t RSF AE t RSF AF t RSF MBF1, MBF2 NOTES: 1. PRS must be HIGH during ...

Page 17

IDT723623/723633/723643 BUS-MATCHING SyncFIFO™ 256 x 36, 512 x 36, 1,024 x 36 CLKA 1 4 RS1 t FSS t FSH SPM t FSS t FSH 0,0 FS1,FS0 FF/IR ENA A0-A35 NOTE: 1. CSA = LOW, W/RA = HIGH, MBA = ...

Page 18

IDT723623/723633/723643 BUS-MATCHING SyncFIFO™ 256 x 36, 512 x 36, 1,024 CLK t t CLKH CLKL CLKA FF/IRA HIGH t ENS1 CSA t ENS1 W/RA t ENS2 MBA t ENS2 ENA t DS A0-A35 NOTE: 1. Written to ...

Page 19

IDT723623/723633/723643 BUS-MATCHING SyncFIFO™ 256 x 36, 512 x 36, 1,024 x 36 CLKB FF/OR HIGH CSB W/RB MBB ENB B0-B17 (Standard Mode) OR B0-B17 (FWFT Mode) NOTE: 1. Unused word B18-B35 are indeterminate. DATA SIZE TABLE FOR WORD READS (1) ...

Page 20

IDT723623/723633/723643 BUS-MATCHING SyncFIFO™ 256 x 36, 512 x 36, 1,024 x 36 CLKB EF/OR HIGH CSB W/RB MBB t ENS2 ENB t MDV t EN B0-B8 (Standard Mode MDV t B0-B8 EN (FWFT Mode) NOTE: 1. Unused bytes ...

Page 21

IDT723623/723633/723643 BUS-MATCHING SyncFIFO™ 256 x 36, 512 x 36, 1,024 x 36 CLKA LOW CSA W/RA HIGH t t ENS2 ENH MBA t t ENS2 ENH ENA IR HIGH A0-A35 W1 t SKEW1 CLKB FIFO Empty ...

Page 22

IDT723623/723633/723643 BUS-MATCHING SyncFIFO™ 256 x 36, 512 x 36, 1,024 x 36 CLKA CSA LOW W/RA HIGH t ENS2 t MBA t ENS2 t ENA FF HIGH A0-A35 W1 t SKEW1 CLKB EF FIFO Empty CSB LOW ...

Page 23

IDT723623/723633/723643 BUS-MATCHING SyncFIFO™ 256 x 36, 512 x 36, 1,024 CLK t t CLKH CLKL CLKB CSB LOW W/RB HIGH LOW MBB t ENS2 ENB OR HIGH B0-B35 Previous Word in FIFO Output Register CLKA FIFO Full ...

Page 24

IDT723623/723633/723643 BUS-MATCHING SyncFIFO™ 256 x 36, 512 x 36, 1,024 CLK t t CLKH CLKL CLKB CSB LOW W/RB HIGH LOW MBB t ENS2 ENB EF HIGH B0-B35 Previous Word in FIFO Output Register CLKA FF FIFO ...

Page 25

IDT723623/723633/723643 BUS-MATCHING SyncFIFO™ 256 x 36, 512 x 36, 1,024 x 36 CLKA t ENS2 ENA AF [D-(Y+1)] Words in FIFO CLKB ENB NOTES: is the minimum time between a rising CLKA edge and a rising CLKB edge for AF ...

Page 26

IDT723623/723633/723643 BUS-MATCHING SyncFIFO™ 256 x 36, 512 x 36, 1,024 x 36 CLKB t ENS1 CSB t ENS1 W/RB t ENS2 MBB t ENS2 ENB B0-B35 CLKA MBF2 CSA W/RA MBA ENA t EN FIFO Output Register A0-A35 NOTE: 1. ...

Page 27

IDT723623/723633/723643 BUS-MATCHING SyncFIFO™ 256 x 36, 512 x 36, 1,024 x 36 PARAMETER MEASUREMENT INFORMATION From Output Timing 1.5 V Input Data, 1.5 V Enable Input VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Enable 1.5 V ...

Page 28

ORDERING INFORMATION XXXXXX Device Type Power Speed Package NOTES: 1. Industrial temperature range is available by special order. 2. Green parts are available. For specific speeds and packages please contact your sales office. DATASHEET DOCUMENT HISTORY 10/04/2000 ...

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