723643L15PF Integrated Device Technology (Idt), 723643L15PF Datasheet - Page 10

• Manufacturer Part Number: 723643L15PF
• Description: FIFO Mem Sync Dual Depth/Width Bi-Dir 1K x 36 128-Pin TQFP
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 723643L15PF

• Package: 128TQFP
• Configuration: Dual
• Bus Directional: Bi-Directional
• Density: 36 Kb
• Organization: 1Kx36
• Data Bus Width: 36 Bit
• Timing Type: Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 5 V
• Operating Temperature: 0 to 70 °C

SIGNAL DESCRIPTION
RESET (RS1/RS2)
pulse to RS1 and RS2 simultaneously. Afterwards, the FIFO memory of the
IDT723623/723633/723643 undergoes a complete reset by taking its Reset
(RS1 and RS2) input LOW for at least four Port A clock (CLKA) and four Port
B clock (CLKB) LOW-to-HIGH transitions. The Reset inputs can switch
asynchronously to the clocks. A Reset initializes the internal read and write
pointers and forces the Full/Input Ready flag (FF/IR) LOW, the Empty/Output
Ready flag (EF/OR) LOW, the Almost-Empty flag (AE) LOW, and the Almost-
Full flag (AF) HIGH. A Reset (RS1) also forces the Mailbox flag (MBF1) of the
parallel mailbox register HIGH, and at the same time the RS2 and MBF2 operate
likewise. After a Reset, the FIFO’s Full/Input Ready flag is set HIGH after two
write clock cycles to begin normal operation.
of the Big-Endian (BE) input for determining the order by which bytes are
transferred through Port B.
values of the Flag Select (FS0, FS1) and Serial Programming Mode (SPM)
inputs for choosing the Almost-Full and Almost-Empty offset programming
method (for details see Table 1, Flag Programming, and Almost-Empty and
Almost-Full flag offset programming section).The relevant Reset timing diagram
can be found in Figure 3.
PARTIAL RESET (PRS)
limited reset by taking its associated Partial Reset (PRS) input LOW for at least
four Port A clock (CLKA) and four Port B clock (CLKB) LOW-to-HIGH transitions.
The Partial Reset input can switch asynchronously to the clocks. A Partial Reset
initializes the internal read and write pointers and forces the Full/Input Ready
flag (FF/IR) LOW, the Empty/Output Ready flag (EF/OR) LOW, the Almost-
Empty flag (AE) LOW, and the Almost-Full flag (AF) HIGH. A Partial Reset also
forces the Mailbox flag (MBF1, MBF2) of the parallel mailbox register HIGH.
After a Partial Reset, the FIFO’s Full/Input Ready flag is set HIGH after two clock
cycles to begin normal operation. See Figure 4, Partial Reset (IDTStandard
and FWFT Modes) for the relevant timing diagram.
mode (FWFT or IDT Standard mode) are currently selected at the time a Partial
Reset is initiated, those settings will be remain unchanged upon completion of
the reset operation. A Partial Reset may be useful in the case where
reprogramming a FIFO following a Reset would be inconvenient.
BIG-ENDIAN/FIRST WORD FALL THROUGH (BE/FWFT)
— ENDIAN SELECTION
active, permitting a choice of Big- or Little-Endian byte arrangement for data read
from Port B. This selection determines the order by which bytes (or words) of
data are transferred through this port. For the following illustrations, assume that
a byte (or word) bus size has been selected for Port B. (Note that when Port
B is configured for a long word size, the Big-Endian function has no application
and the BE input is a “don’t care”
NOTE:
1. Either a HIGH or LOW can be applied to a “don’t care” input with no change to the logical operation of the FIFO. Nevertheless, inputs that are temporarily “don’t care” (along with unused
IDT723623/723633/723643 BUS-MATCHING SyncFIFO™
256 x 36, 512 x 36, 1,024 x 36
inputs) must not be left open, rather they must be either HIGH or LOW.
After power up, a Reset operation must be performed by providing a LOW
A LOW-to-HIGH transition on the FlFO Reset (RS1) input latches the value
A LOW-to-HIGH transition on the FlFO Reset (RS1) input also latches the
The FIFO memory of the IDT723623/723633/723643 undergoes a
Whatever flag offsets, programming method (parallel or serial), and timing
This is a dual purpose pin. At the time of Reset, the BE select function is
1
.)
10
LOW to HIGH will select a Big-Endian arrangement. In this case, the most
significant byte (word) of the long word written to Port A will be read from Port
B first; the least significant byte (word) of the long word written to Port A will be
read from Port B last.
to HIGH will select a Little-Endian arrangement. In this case, the least significant
byte (word) of the long word written to Port A will be read from Port B first; the
most significant byte (word) of the long word written to Port A will be read from
Port B last. Refer to Figure 2 for an illustration of the BE function. See Figure
3 (Reset) for an Endian select timing diagram.
— TIMING MODE SELECTION
two possible timing modes: IDT Standard mode or First Word Fall Through
(FWFT) mode. Once the Reset (RS1) input is HIGH, a HIGH on the BE/FWFT
input during the next LOW-to-HIGH transition of CLKA and CLKB will select IDT
Standard mode. This mode uses the Empty Flag function (EF) to indicate
whether or not there are any words present in the FIFO memory. It uses the
Full Flag function (FF) to indicate whether or not the FIFO memory has any free
space for writing. In IDT Standard mode, every word read from the FIFO,
including the first, must be requested using a formal read operation.
the next LOW-to-HIGH transition of CLKA and CLKB will select FWFT mode.
This mode uses the Output Ready function (OR) to indicate whether or not there
is valid data at the data outputs (B0-B35). It also uses the Input Ready function
(IR) to indicate whether or not the FIFO memory has any free space for writing.
In the FWFT mode, the first word written to an empty FIFO goes directly to data
outputs, no read request necessary. Subsequent words must be accessed by
performing a formal read operation.
desired timing mode must remain static throughout FIFO operation. Refer to
Figure 3 (Reset) for a First Word Fall Through select timing diagram.
PROGRAMMING THE ALMOST-EMPTY AND ALMOST-FULL FLAGS
offset values for the Almost-Empty and Almost-Full flags. The Almost-Empty flag
(AE) Offset register is labeled X and Almost-Full flag (AF) Offset register is labeled
Y. The offset registers can be loaded with preset values during the reset of the
FIFO, programmed in parallel using the FIFO’s Port A data inputs, or
programmed in serial using the Serial Data (SD) input (see Table 1). SPM, FS0/
SD and FS1/SEN function the same way in both IDT Standard and FWFT
modes.
— PRESET VALUES
with one of the three preset values listed in Table 1, the Serial Program Mode
(SPM) and at least one of the flag-select inputs must be HIGH during the LOW-
to-HIGH transition of the Reset input (RS1). For example, to load the preset
value of 64 into X and Y, SPM, FS0 and FS1 must be HIGH when RS1 returns
HIGH. For the relevant preset value loading timing diagram, see Figure 3.
After Reset, the FWFT select function is active, permitting a choice between
Following Reset, the level applied to the BE/FWFT input to choose the
Two registers in the IDT723623/723633/723643 are used to hold the
To load a FIFO’s Almost-Empty flag and Almost-Full flag Offset registers
A HIGH on the BE/FWFT input when the Reset (RS1) input goes from
A LOW on the BE/FWFT input when the Reset (RS1) input goes from LOW
Once the Reset (RS1) input is HIGH, a LOW on the BE/FWFT input during
COMMERCIAL TEMPERATURE RANGE