M25PE16-VMP6G NUMONYX, M25PE16-VMP6G Datasheet - Page 25

• Manufacturer Part Number: M25PE16-VMP6G
• Description: Flash Mem Serial-SPI 3.3V 16M-Bit 2M x 8 8ns 8-Pin VFQFPN EP Tube
• Manufacturer: NUMONYX

Specifications of M25PE16-VMP6G

• Package: 8VFQFPN EP
• Cell Type: NOR
• Density: 16 Mb
• Architecture: Sectored
• Block Organization: Symmetrical
• Typical Operating Supply Voltage: 3.3 V
• Sector Size: 64KByte x 32
• Timing Type: Synchronous
• Operating Temperature: -40 to 85 °C
• Interface Type: Serial-SPI

M25PE16
6.4
6.4.1
6.4.2
6.4.3
6.4.4
Read status register (RDSR)
The read status register (RDSR) instruction allows the status register to be read. The status
register may be read at any time, even while a program, erase or write cycle is in progress.
When one of these cycles is in progress, it is recommended to check the write in progress
(WIP) bit before sending a new instruction to the device. It is also possible to read the status
register continuously, as shown in
The status bits of the status register are as follows:
WIP bit
The write in progress (WIP) bit indicates whether the memory is busy with a write, program
or erase cycle. When set to ‘1’, such a cycle is in progress, when reset to ‘0’ no such cycle is
in progress.
WEL bit
The write enable latch (WEL) bit indicates the status of the internal write enable latch. When
set to ‘1’ the internal write enable latch is set, when set to ‘0’ the internal write enable latch is
reset and no write, program or erase instruction is accepted.
BP2, BP1, BP0 bits
The block protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the area to
be software protected against program and erase instructions. These bits are written with
the write status register (WRSR) instruction. When one or more of the block protect (BP2,
BP1, BP0) bits is set to ‘1’, the relevant memory area (as defined in
protected against page program (PP), sector erase (SE) and subsector erase (SSE)
instructions. The block protect (BP2, BP1, BP0) bits can be written provided that the
hardware protected mode has not been set. The bulk erase (BE) instruction is executed if,
and only if:
SRWD bit
The status register write disable (SRWD) bit is operated in conjunction with the Write
Protect (W) signal. When the status register write disable (SRWD) bit is set to ‘1’, and Write
Protect (W) is driven Low, the non-volatile bits of the status register (SRWD, BP2, BP1, BP0)
become read-only bits. In such a state, as the write status register (WRSR) instruction is no
longer accepted for execution, the definition of the size of the write protected area cannot be
further modified.
Table 7.
1. WEL (write enable latch) and WIP ((write in progress) are volatile read-only bits (WEL is set and reset by
2. SRWD = status register write protect bit; BP0, BP1, BP2 = block protect bits.
SRWD
specific instructions; WIP is automatically set and reset by the internal logic of the device).
b7
all block protect (BP2, BP1, BP0) bits are 0
the lock register protection bits are not all set (‘1’)
Status register format
0
0
Figure
(1) (2)
BP2
9.
BP1
BP0
Table
WEL
3) becomes
Instructions
WIP
b0
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