C8051F066-GQ Silicon Laboratories Inc, C8051F066-GQ Datasheet - Page 317
![MCU 8-Bit C8051F06x 8051 CISC 32KB Flash 3.3V 100-Pin TQFP](/photos/12/39/123961/c8051f066-gq_sml.jpg)
C8051F066-GQ
Manufacturer Part Number
C8051F066-GQ
Description
MCU 8-Bit C8051F06x 8051 CISC 32KB Flash 3.3V 100-Pin TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F06xr
Specifications of C8051F066-GQ
Package
100TQFP
Device Core
8051
Family Name
C8051F06x
Maximum Speed
25 MHz
Operating Supply Voltage
3.3 V
Data Bus Width
8 Bit
Number Of Programmable I/os
59
Interface Type
I2C/SMBus/SPI/UART
On-chip Adc
2-chx16-bit
Number Of Timers
5
Ram Size
4.25 KB
Program Memory Size
32 KB
Program Memory Type
Flash
Operating Temperature
-40 to 85 °C
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
59
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 2x16b
Oscillator Type
Internal
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
336-1221
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F066-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Company:
Part Number:
C8051F066-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
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26.
Each MCU has an on-chip JTAG interface and logic to support boundary scan for production and in-sys-
tem testing, Flash read/write operations, and non-intrusive in-circuit debug. The JTAG interface is fully
compliant with the IEEE 1149.1 specification. Refer to this specification for detailed descriptions of the Test
Interface and Boundary-Scan Architecture. Access of the JTAG Instruction Register (IR) and Data Regis-
ters (DR) are as described in the Test Access Port and Operation of the IEEE 1149.1 specification.
The JTAG interface is accessed via four dedicated pins on the MCU: TCK, TMS, TDI, and TDO.
Through the 16-bit JTAG Instruction Register (IR), any of the eight instructions shown in Figure 26.1 can
be commanded. There are three DR’s associated with JTAG Boundary-Scan, and four associated with
Flash read/write operations on the MCU.
IR Value
0xFFFF
0x0000
0x0002
0x0004
0x0082
0x0083
0x0084 Flash Address
0x0085
Bit15
JTAG (IEEE 1149.1)
Flash Control
Flash Scale
Instruction
Flash Data
PRELOAD
SAMPLE/
EXTEST
IDCODE
BYPASS
Selects FLASHSCL Register which controls the Flash one-shot timer and
Selects FLASHCON Register to control how the interface logic responds
Selects FLASHADR Register which holds the address of all Flash read,
Figure 26.1. IR: JTAG Instruction Register
Selects the Boundary Data Register for observability and presetting the
Selects FLASHDAT Register for reads and writes to the Flash memory
Selects the Boundary Data Register for control and observability of all
to reads and writes to the FLASHDAT Register
Rev. 1.2
Selects Bypass Data Register
write, and erase operations
Selects device ID Register
C8051F060/1/2/3/4/5/6/7
read-always enable
scan-path latches
Description
device pins
Bit0
Reset Value
0x0000
317
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