P89V51RD2FBC NXP Semiconductors, P89V51RD2FBC Datasheet - Page 50

• Manufacturer Part Number: P89V51RD2FBC
• Description: MCU 8-Bit 89V 80C51 CISC 64KB Flash 5V 44-Pin TQFP Tray
• Manufacturer: NXP Semiconductors

Specifications of P89V51RD2FBC

• Package: 44TQFP
• Device Core: 80C51
• Family Name: 89V
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 32
• Interface Type: SPI/UART
• Number Of Timers: 3
• Ram Size: 1 KB
• Program Memory Size: 64 KB
• Program Memory Type: Flash
• Operating Temperature: -40 to 85 °C

NXP Semiconductors
Table 42.
P89V51RB2_RC2_RD2_5
Product data sheet
ECOMn
0
x
x
x
1
1
1
1
CAPPn
0
1
0
1
0
0
0
0
PCA module modes (CCAPMn register)
6.9.1 PCA capture mode
CAPNn
0
0
1
1
0
0
0
0
Table 41.
To use one of the PCA modules in the capture mode
CCAPM bits CAPN and CAPP for that module must be set. The external CEX input for the
module (on port 1) is sampled for a transition. When a valid transition occurs the PCA
hardware loads the value of the PCA counter registers (CH and CL) into the module’s
capture registers (CCAPnL and CCAPnH).
Bit
2
1
0
MATn
0
0
0
0
1
1
0
1
CCAPMn - PCA modules compare/capture register (address CCAPM0 0DAH,
CCAPM1 0DBH, CCAPM2 0DCH, CCAPM3 0DDH, CCAPM4 0DEH) bit description
Symbol
TOGn
PWMn
ECCFn
TOGn
0
0
0
0
0
1
0
x
Rev. 05 — 12 November 2009
Description
Toggle. When TOGn = 1, a match of the PCA counter with this
module’s compare/capture register causes the CEXn pin to toggle.
Pulse Width Modulation mode. PWMn = 1 enables the CEXn pin to be
used as a pulse width modulated output.
Enable CCF Interrupt. Enables compare/capture flag CCFn in the
CCON register to generate an interrupt.
PWMn
0
0
0
0
0
0
1
0
ECCFn
0
x
x
x
x
x
0
x
P89V51RB2/RC2/RD2
no operation
16-bit capture by a positive-edge trigger on
16-bit capture by a negative-edge trigger on
16-bit capture by any transition on CEXn
16-bit software timer
16-bit high-speed output
8-bit PWM
Watchdog timer
Module function
CEXn
CEXn
8-bit microcontrollers with 80C51 core
(Figure
23) either one or both of the
© NXP B.V. 2009. All rights reserved.
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