EP7311-CV Cirrus Logic Inc, EP7311-CV Datasheet - Page 46

• Manufacturer Part Number: EP7311-CV
• Description: Low-Power Processor 208-Pin LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP7r

Specifications of EP7311-CV

• Core Processor: ARM7
• Core Size: 32-Bit
• Speed: 74MHz
• Connectivity: Codec, EBI/EMI, IrDA, Keypad, Multimedia Codec, SPI/Microwire1, UART/USART
• Peripherals: LCD, LED, MaverickKey, PWM
• Number Of I /o: 27
• Program Memory Type: ROMless
• Ram Size: 56K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 2.7 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-LQFP
• Processor Series: EP73xx
• Core: ARM720T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: No
• Other names: 598-1224

EP7311
High-Performance, Low-Power System on Chip
256-Ball PBGA Ball Listing
The list is ordered by ball location.
46
Ball Location
A10
A11
A12
A13
A14
A15
A16
B10
B11
B12
B13
B14
B15
B16
C10
C11
A1
A2
A3
A4
A5
A6
A7
A8
A9
B1
B2
B3
B4
B5
B6
B7
B8
B9
C1
C2
C3
C4
C5
C6
C7
C8
C9
nMOE/nSDCAS
MOSCOUT
VDDCORE
nURESET
nSDCS[1]
VDDOSC
WAKEUP
SDQM[3]
Table V. 256-Ball PBGA Ball Listing
EXPCLK
VDDIO
SDCLK
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
nCS[4]
nCS[1]
VSSIO
nCS[5]
nCS[3]
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
Name
DD[1]
DD[2]
CL[1]
D[0]
D[2]
A[3]
A[6]
D[1]
A[2]
A[4]
A[5]
M
Pad ground I/O ground
Core power Digital core power, 2.5V
Pad ground I/O ground
Pad ground I/O ground
Pad ground I/O ground
Pad ground I/O ground
Pad ground I/O ground
Pad ground I/O ground
Pad ground I/O ground
Pad power
Pad power
Pad power
Pad power
Pad power
Pad power
Pad power
Pad power
Pad power
Oscillator
power
Type
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
Digital I/O power, 3.3V
Chip select out
Chip select out
SDRAM clock out
SDRAM byte lane mask
LCD serial display data
LCD AC bias drive
Digital I/O power, 3.3V
Data I/O
Data I/O
System byte address
Digital I/O power, 3.3V
System byte address
Main oscillator out
Oscillator power in, 2.5V
Chip select out
I/O ground
Chip select out
ROM, expansion OP enable/SDRAM
CAS control signal
Digital I/O power, 3.3V
SDRAM chip select out
LCD serial display data
LCD line clock
Data I/O
System byte address
System byte address
System byte address
System wake up input
Digital I/O power, 3.3V
User reset input
Digital I/O power, 3.3V
Expansion clock input
Digital I/O power, 3.3V
Digital I/O power, 3.3V
Description
©
Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
Ball Location
C12
C13
C14
C15
C16
D10
D11
D12
D13
D14
D15
D16
E10
E11
E12
E13
E14
E15
E16
D1
D2
D3
D4
D5
D6
D7
D8
D9
E1
E2
E3
E4
E5
E6
E7
E8
E9
F1
F2
F3
F4
F5
F6
Table V. 256-Ball PBGA Ball Listing (Continued)
nMEDCHG/nBROM
WRITE/nSDRAS
nMWE/nSDWE
RUN/CLKEN
nEXTPWR
nSDCS[0]
SDQM[2]
VSSOSC
EXPRDY
VSSRTC
nPWRFL
MOSCIN
VDDIO
VDDIO
VDDIO
RXD[2]
WORD
VDDIO
TXD[2]
VSSIO
VSSIO
VSSIO
nCS[2]
VSSIO
VSSIO
nCS[0]
VSSIO
VSSIO
VSSIO
Name
nPOR
CL[2]
PB[7]
D[10]
PB[5]
PB[3]
FRM
D[4]
D[7]
D[8]
A[0]
D[5]
D[9]
TDI
Core ground Real time clock ground
Pad ground I/O ground
Pad ground I/O ground
Pad ground I/O ground
Pad ground I/O ground
Pad ground I/O ground
Pad ground I/O ground
Pad ground I/O ground
Pad ground I/O ground
Pad power
Pad power
Pad power
Pad power
Oscillator
ground
Type
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
Digital I/O power, 3.3V
Power-on reset input
External power supply sense input
Transfer direction / SDRAM RAS signal
output
Expansion port ready input
Digital I/O power, 3.3V
Chip select out
ROM, expansion write enable/ SDRAM
write enable control signal
SDRAM chip select out
LCD pixel clock out
Data I/O
Power fail sense input
Main oscillator input
Digital I/O power, 3.3V
Data I/O
Data I/O
UART 2 receive data input
GPIO port B
JTAG data input
Word access select output
Chip select out
SDRAM byte lane mask
LCD frame synchronization pulse
System byte address
Data I/O
PLL ground
Media change interrupt input / internal
ROM boot enable
Digital I/O power, 3.3V
Data I/O
Data I/O
GPIO port B
GPIO port B
UART 2 transmit data output
Run output / clock enable output
Description
DS506F1