XC2C32A-6CPG56I Xilinx Inc, XC2C32A-6CPG56I Datasheet
XC2C32A-6CPG56I
Specifications of XC2C32A-6CPG56I
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XC2C32A-6CPG56I Summary of contents
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... Open-drain output option for Wired-OR and LED drive - Optional bus-hold, 3-state or weak pullup on select I/O pins - Optional configurable grounds on unused I/Os - Mixed I/O voltages compatible with 1.5V, 1.8V, 2.5V, and 3.3V logic levels on all parts Table 1: CoolRunner-II CPLD Family Parameters XC2C32A Macrocells 32 Max I (ns) 3 (ns) 1 ...
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... I/O count. All packages are surface mount, with over half of them being ball-grid technologies. The ultra tiny packages permit maximum functional capacity in the smallest possible area. The CMOS technology used Table 3: CoolRunner-II CPLD Family Packages and I/O Count XC2C32A XC2C64A (1) QFG32 21 ...
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... R the same V level. (See Table 5 CCIO CoolRunner-II CPLD I/O standards.) Table 4: CoolRunner-II CPLD Family Features XC2C32A ✓ IEEE 1532 I/O banks 2 Clock division - ✓ DualEDGE Registers DataGATE - ✓ LVTTL ✓ LVCMOS33, 25, (1) 18, and 15 SSTL2_1 - SSTL3_1 - HSTL_1 - ✓ Configurable ground ✓ Quadruple data security ✓ ...
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CoolRunner-II CPLD Family path. The BSC and ISP block has the JTAG controller and In-System Programming Circuits. MC1 I/O Pin MC2 I/O Pin 16 MC16 I/O Pin 16 JTAG BSC and ISP Function Block The CoolRunner-II CPLD FBs contain 16 ...
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R Macrocell The CoolRunner-II CPLD macrocell is extremely efficient and streamlined for logic creation. Users can develop sum of product (SOP) logic expressions that comprise inputs and span 56 product terms within a single function block. The ...
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CoolRunner-II CPLD Family software. The AIM minimizes both propagation delay and power as it makes attachments to the various FBs. I/O Block I/O blocks are primarily transceivers. However, each I/O is either automatically compliant with standard voltage ranges or can ...
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... CPLDs are widely used as voltage interface translators. To that end, the output pins are grouped in large banks. The XC2C32A, XC2C64A, XC2C128 and XC2C256 devices support two output banks. With two, the outputs switch to one of two selected output voltage levels, unless both banks are set to the same voltage ...
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CoolRunner-II CPLD Family nally generated DataGATE control logic can be assigned to this I/O pin with the BUFG=DATA_GATE attribute. Latch Latch Figure 6: DataGATE Architecture (output drivers not shown) Global Signals Global signals, clocks (GCK), sets/resets (GSR), and output enables ...
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R Additional Clock Options: Division, DualEDGE, and CoolCLOCK Clock Divider A clock divider circuit has been included in the CoolRunner-II CPLD architecture to divide one externally supplied global clock by standard values. The allowable val- ues for the division are ...
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CoolRunner-II CPLD Family CLK_CT PTC Figure 9: Macrocell Clock Chain with DualEDGE Option Shown GCK2 Synch Reset Figure 10: CoolCLOCK Created by Cascading Clock Divider and DualEDGE Option Design Security Designs can be secured during programming to prevent either accidental ...
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R Timing Model Figure 11 shows the CoolRunner-II CPLD timing model. It represents one aspect of the overall architecture from a tim- ing viewpoint. Each little block is a time delay that a signal incurs if the signal passes through ...
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CoolRunner-II CPLD Family Programming The programming data sequence is delivered to the device using either Xilinx iMPACT software and a Xilinx download cable, a third-party JTAG development JTAG-compatible board tester simple microprocessor interface that emulates the JTAG instruction ...
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... IOB Bus-Hold/Weak Pullup Device Outputs Device Inputs and Clocks Function Block JTAG Controller I/O Banking CoolRunner-II CPLD XC2C32A and XC2C64A macrocell parts support two V rails that can range from 3.3V CCIO down to 1.5V operation. Two V CCIO the 128 and 256 macrocell parts where outputs on each rail can independently range from 3 ...
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CoolRunner-II CPLD Family Absolute Maximum Ratings Symbol (2) V Supply voltage relative to GND CC (3) V Input voltage relative to GND I T Ambient Temperature (C-grade) A Ambient Temperature (I-grade) (4) T Maximum junction temperature J T Storage temperature ...
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... Incorporate links to Data Sheets, Application Notes, and Device Packages 02/26/04 1.9 Change to Power-Up Characteristics, page 11. Change T I/O compatibility information. Added T 05/21/04 2.0 Add XC2C32A and XC2C64A devices. 07/30/04 2.1 Pb-free documentation. Changes to T 01/10/05 2.2 Added information about programming options, page 11. ...
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CoolRunner-II CPLD Family Date Version 04/15/05 2.4 Change to F 06/28/05 2.5 Move to Product Specification 03/20/06 2.6 Add Warranty Disclaimer; modified Global Signals section to say that GCK, GSR and GTS can be used as general purpose I/O. 07/24/06 ...