XC2C64 Xilinx, XC2C64 Datasheet
XC2C64
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XC2C64 Summary of contents
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... The design features are supported starting with Xil- inx ISE 4.1i, WebFITTER, and ISE WebPACK. Additional details can be found in Table 1 shows the macrocell capacity and key timing parameters for the CoolRunner-II CPLD family. XC2C64 XC2C128 XC2C256 64 128 256 64 ...
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... CoolRunner-II I/O standards.) The clock division capability is less efficient on small parts, but more useful and likely to be used on larger ones. DataGATE, an ability to block and latch inputs to save power, is valuable in larger parts, but brings marginal benefit to small parts. XC2C32 XC2C64 XC2C128 ...
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... CPLDs. The underlying architecture is a traditional CPLD architecture combining macrocells into Function Blocks (FBs) interconnected with a global routing matrix, the Xilinx Advanced Interconnect Matrix (AIM). The Func- tion Blocks use a Programmable Logic Array (PLA) config- uration which allows all product tems to be routed and shared among any of the macrocells of the FB ...
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... Out penalty to route signals to another FB to continue creating To AIM logic. Xilinx design software handles all this automatically. Macrocell The CoolRunner-II CPLD macrocell is extremely efficient and streamlined for logic creation. Users can develop sum ...
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... These I/O standards all require VREF pins for proper operation. The CoolRunner-II CPLD allows any I/O pin to act as a VREF pin, granting the board layout engineer extra freedom when laying out the www.xilinx.com 1-800-255-7778 CoolRunner-II CPLD Family Feedback to AIM ...
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... This kind of flexibility permits easy interfacing to 3.3V, 2.5V, 1.8V, and 1. single part has pin-range requirements that must be observed. REF The Xilinx software aids designers in remaining within the proper pin range. Available on 128 Macrocell Devices and Larger Hysteresis CTE V CCIO PTB ...
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... If DataGATE is not needed, this pin is an ordinary I/O. Figure 5: CMOS I DataGATE Assertion Rail MC1 MC2 PLA PLA To AIM MC16 AIM MC1 MC2 PLA PLA To AIM MC16 www.xilinx.com 1-800-255-7778 CoolRunner-II CPLD Family Frequency DS090_05_101001 vs. Switching Frequency Curve CC MC1 MC2 Latch To AIM Latch To AIM MC16 ...
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... CoolCLOCK is created by internal clock cascading with the divider and DualEDGE flip-flop working together Clock CDRST Figure 8: Clock Division Circuitry for GCK2 www.xilinx.com 1-800-255-7778 Figure 8). This capability is supplied on Figure 9 shows the macrocell flip-flop Figure 10 shows DS090_08_121201 DS090 (v1.7) October 2, 2003 Preliminary Product Specification R ...
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... Equations for the higher level tim- ing values (i.e., T summarizes the individual parameters and provides a brief definition of their associated functions. Xilinx application note XAPP375 details the CoolRunner-II CPLD family tim- ing with several examples. www.xilinx.com ...
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... Figure 11: CoolRunner-II CPLD Timing Model Table 5: Timing Parameter Definitions (Continued) Symbol Macrocell Delays T PDI T SUI ECSU T ECHO T COI T AOI T HYS Feedback Delays OEM www.xilinx.com 1-800-255-7778 F F PDI PDI T T COI COI ECSU ECSU OUT OUT ECHO ...
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... On-The-Fly Reconfiguration (OTF) Xilinx ISE 5.2i supports OTF for CoolRunner-II CPLDs. This permits programming a new nonvolatile pattern into the part while another pattern is currently in use. OTF has the same voltage and temperature specifications as system program- ming ...
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... Development System Support Xilinx CoolRunner-II CPLDs are supported by all configura- tions of Xilinx standard release development software as well as the freely available WebFITTER and ISE WebPACK software available from www.xilinx.com. Third party devel- opment tools include synthesis tools from Cadence, Exem- plar, Mentor Graphics, Synplicity, and Synopsys ...
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... Speed CoolRunner-II Data Sheets (Cross Point http://direct.xilinx.com/bvdocs/publications/ds090.pdf (CoolRunner-II Family Datasheet) (Demo Board) http://direct.xilinx.com/bvdocs/publications/ds091.pdf (I/O (XC2C32 Datasheet) http://direct.xilinx.com/bvdocs/publications/ds092.pdf (Single Error (XC2C64 Datasheet) http://direct.xilinx.com/bvdocs/publications/ds093.pdf (DDR SDRAM (XC2C128 Datasheet) http://direct.xilinx.com/bvdocs/publications/ds094.pdf (PicoBlaze (XC2C256 Datasheet) http://direct.xilinx.com/bvdocs/publications/ds095.pdf (XC2C384 Datasheet) www.xilinx.com 1-800-255-7778 CoolRunner-II CPLD Family Min ...
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... CoolRunner-II CPLD Family http://direct.xilinx.com/bvdocs/publications/ds096.pdf (XC2C512 Datasheet) Revision History The following table shows the revision history for this document. Date Version 01/03/02 1.0 Initial Xilinx release 07/04/02 1.1 Revisions and updates 07/24/02 1.2 Revisions and updates 09/24/02 1.3 Additions to "Power Characteristics" section 01/28/03 1.4 Addition of the "Further Reading" section 02/26/03 1.5 Multiple minor revisions 03/12/03 1 ...