XC2S100E-6FT256I Xilinx Inc, XC2S100E-6FT256I Datasheet - Page 11

• Manufacturer Part Number: XC2S100E-6FT256I
• Description: FPGA Spartan®-IIE Family 100K Gates 2700 Cells 357MHz 0.15um Technology 1.8V 256-Pin FTBGA
• Manufacturer: Xilinx Inc

Specifications of XC2S100E-6FT256I

• Package: 256FTBGA
• Family Name: Spartan®-IIE
• Device Logic Cells: 2700
• Device Logic Units: 600
• Device System Gates: 100000
• Maximum Internal Frequency: 357 MHz
• Typical Operating Supply Voltage: 1.8 V
• Maximum Number Of User I/os: 182
• Ram Bits: 40960

Optional pull-up and pull-down resistors and an optional
weak-keeper circuit are attached to each user I/O pad. Prior
to configuration all outputs not involved in configuration are
forced into their high-impedance state. The pull-down resis-
tors and the weak-keeper circuits are inactive, but inputs
may optionally be pulled up. The activation of pull-up resis-
tors prior to configuration is controlled on a global basis by
the configuration mode pins. If the pull-up resistors are not
activated, all the pins will float. Consequently, external
pull-up or pull-down resistors must be provided on pins
required to be at a well-defined logic level prior to configura-
tion.
All pads are protected against damage from electrostatic
discharge (ESD) and from over-voltage transients. After
configuration, clamping diodes are connected to V
LVTTL, PCI, HSTL, SSTL, CTT, and AGP standards.
All Spartan-IIE FPGA IOBs support IEEE 1149.1-compati-
ble boundary scan testing.
Input Path
A buffer in the IOB input path routes the input signal directly
to internal logic and through an optional input flip-flop.
An optional delay element at the D-input of this flip-flop elim-
inates pad-to-pad hold time. The delay is matched to the
internal clock-distribution delay of the FPGA, and when
used, assures that the pad-to-pad hold time is zero.
Each input buffer can be configured to conform to any of the
low-voltage signaling standards supported. In some of
these standards the input buffer utilizes a user-supplied
threshold voltage, V
constraints on which standards can used in close proximity
to each other. See
There are optional pull-up and pull-down resistors at each
input for use after configuration.
Output Path
The output path includes a 3-state output buffer that drives
the output signal onto the pad. The output signal can be
routed to the buffer directly from the internal logic or through
an optional IOB output flip-flop.
The 3-state control of the output can also be routed directly
from the internal logic or through a flip-flip that provides syn-
chronous enable and disable.
Each output driver can be individually programmed for a
wide range of low-voltage signaling standards. Each output
buffer can source up to 24 mA and sink up to 48 mA. Drive
strength and slew rate controls minimize bus transients. The
default output driver is LVTTL with 12 mA drive strength and
slow slew rate.
In most signaling standards, the output high voltage
depends on an externally supplied V
to supply V
DS077-2 (v2.3) June 18, 2008
Product Specification
CCO
R
imposes constraints on which standards
I/O
REF
Banking.
. The need to supply V
CCO
voltage. The need
REF
imposes
CCO
www.xilinx.com
for
can be used in close proximity to each other. See
ing.
An optional weak-keeper circuit is connected to each out-
put. When selected, the circuit monitors the voltage on the
pad and weakly drives the pin High or Low to match the
input signal. If the pin is connected to a multiple-source sig-
nal, the weak keeper holds the signal in its last state if all
drivers are disabled. Maintaining a valid logic level in this
way helps eliminate bus chatter.
Because the weak-keeper circuit uses the IOB input buffer
to monitor the input level, an appropriate V
be provided if the signaling standard requires one. The pro-
vision of this voltage must comply with the I/O banking
rules.
I/O Banking
Some of the I/O standards described above require V
and/or V
plied and connected to device pins that serve groups of
IOBs, called banks. Consequently, restrictions exist about
which I/O standards can be combined within a given bank.
Eight I/O banks result from separating each edge of the
FPGA into two banks (see
show the bank affiliation of each I/O (see
page
connected to the same voltage. Voltage requirements are
determined by the output standards in use.
In the TQ144 and PQ208 packages, the eight banks have
V
allowed in these packages, although different V
are allowed in each of the eight banks.
Within a bank, standards may be mixed only if they use the
same V
GTL and GTL+ appear under all voltages because their
open-drain outputs do not depend on V
CCO
53). Each bank has multiple V
Spartan-IIE FPGA Family: Functional Description
connected together. Thus, only one V
CCO
REF
. Compatible standards are shown in
Figure 5: Spartan-IIE I/O Banks
voltages. These voltages are externally sup-
Bank 0
Bank 5
GCLK3
GCLK1
Spartan-IIE
Device
Figure
GCLK2
GCLK0
CCO
Bank 1
Bank 4
5). The pinout tables
CCO
pins which must be
REF
. Note that V
DS077-2_02_051501
Pinout Tables,
voltage must
CCO
REF
I/O Bank-
Table
level is
values
CCO
CCO
11
4.