XC2S100E-6FT256I Xilinx Inc, XC2S100E-6FT256I Datasheet - Page 60

• Manufacturer Part Number: XC2S100E-6FT256I
• Description: FPGA Spartan®-IIE Family 100K Gates 2700 Cells 357MHz 0.15um Technology 1.8V 256-Pin FTBGA
• Manufacturer: Xilinx Inc

Specifications of XC2S100E-6FT256I

• Package: 256FTBGA
• Family Name: Spartan®-IIE
• Device Logic Cells: 2700
• Device Logic Units: 600
• Device System Gates: 100000
• Maximum Internal Frequency: 357 MHz
• Typical Operating Supply Voltage: 1.8 V
• Maximum Number Of User I/os: 182
• Ram Bits: 40960

Spartan-IIE FPGA Family: Pinout Tables
TQ144 Pinouts (XC2S50E and XC2S100E)
60
I/O (CS),
L5P_YY
I/O (WRITE),
L5N_YY
I/O
I/O, VREF
Bank 1
I/O
I/O, L4P_YY
I/O, L4N_YY
GND
VCCINT
I/O, L3P_YY
I/O, L3N_YY
I/O, VREF
Bank 1
I/O
I/O (DLL), L2P
GCK2, I
GND
VCCO
GCK3, I
VCCINT
I/O (DLL), L2N
I/O, VREF
Bank 0
I/O, L1P_YY
I/O, L1N_YY
VCCINT
GND
I/O, L0P_YY
I/O, L0N_YY
(Continued)
Function
Pad Name
Bank
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
-
-
-
-
-
-
-
P112
P113
P114
P115
P116
P117
P118
P119
P120
P121
P122
P123
P124
P125
P126
P127
P128
P129
P130
P131
P132
P133
P134
P135
P136
P137
P138
Pin
Async.
Output
Option
LVDS
All
All
All
All
All
All
All
All
All
All
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
XC2S100E
XC2S100E
Option
V
All
All
All
REF
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
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TQ144 Pinouts (XC2S50E and XC2S100E)
TQ144 Differential Clock Pins
I/O
I/O, VREF
Bank 0
I/O
I/O
TCK
VCCO
GCK0
GCK1
GCK2
GCK3
(Continued)
Clock
Function
Pad Name
Bank
4
5
1
0
Bank
P126
P129
P55
P52
Pin
0
0
0
0
-
-
P
P139
P140
P141
P142
P143
P144
GCK0, I
GCK1, I
GCK2, I
GCK3, I
Pin
Name
DS077-4 (2.3) June 18, 2008
Async.
Output
Option
LVDS
P125
P131
Product Specification
P56
P50
Pin
-
-
-
-
-
-
N
I/O (DLL),
I/O (DLL),
I/O (DLL),
I/O (DLL),
Name
Option
L17N
L17P
L2P
L2N
V
All
REF
-
-
-
-
-
R