XC2V1000-5FG456I Xilinx Inc, XC2V1000-5FG456I Datasheet - Page 85

• Manufacturer Part Number: XC2V1000-5FG456I
• Description: FPGA Virtex-II™ Family 1M Gates 11520 Cells 750MHz 0.15um/0.12um (CMOS) Technology 1.5V 456-Pin FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-IIr

Specifications of XC2V1000-5FG456I

• Package: 456FBGA
• Family Name: Virtex-II™
• Device Logic Units: 11520
• Device System Gates: 1000000
• Number Of Registers: 10240
• Maximum Internal Frequency: 750 MHz
• Typical Operating Supply Voltage: 1.5 V
• Maximum Number Of User I/os: 324
• Ram Bits: 737280
• Number Of Labs/clbs: 1280
• Total Ram Bits: 737280
• Number Of I /o: 324
• Number Of Gates: 1000000
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 456-BBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Logic Elements/cells: -
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Output Clock Jitter
Table 40: Output Clock Jitter
Output Clock Phase Alignment
Table 41: Output Clock Phase Alignment
DS031-3 (v3.5) November 5, 2007
Product Specification
Notes:
1. Values for this parameter are available at www.xilinx.com.
Notes:
1. "DLL outputs" is used here to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
2. CLKOUT_DUTY_CYCLE_DLL applies to the 1X clock outputs (CLK0, CLK90, CLK180, and CLK270) only if
3. Specification also applies to PSCLK.
Clock Synthesis Period Jitter
CLK0
CLK90
CLK180
CLK270
CLK2X, CLK2X180
CLKDV (integer division)
CLKDV (non-integer division)
CLKFX, CLKFX180
Phase Offset Between CLKIN and CLKFB
CLKIN/CLKFB
Phase Offset Between Any DCM Outputs
All CLK outputs
Duty Cycle Precision
DLL outputs
CLKFX outputs
DUTY_CYCLE_CORRECTION = TRUE.
Description
Description
(1)
R
CLKIN_CLKFB_PHASE
CLKOUT_PHASE
CLKOUT_DUTY_CYCLE_DLL
CLKOUT_DUTY_CYCLE_FX
CLKOUT_PER_JITT_0
CLKOUT_PER_JITT_90
CLKOUT_PER_JITT_180
CLKOUT_PER_JITT_270
CLKOUT_PER_JITT_2X
CLKOUT_PER_JITT_DV1
CLKOUT_PER_JITT_DV2
CLKOUT_PER_JITT_FX
Symbol
Symbol
www.xilinx.com
(2)
Virtex-II Platform FPGAs: DC and Switching Characteristics
Constraints
Constraints
±140
±150
±100
Note 1
±50
±100
±150
±150
±150
±200
±150
±300
-6
-6
Speed Grade
Speed Grade
Note 1
±140
±150
±100
±100
±150
±150
±150
±200
±150
±300
±50
-5
-5
Note 1
±140
±150
±100
±100
±150
±150
±150
±200
±150
±300
±50
-4
-4
Module 3 of 4
Units
Units
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
37