XC2V500-6FG456C Xilinx Inc, XC2V500-6FG456C Datasheet - Page 60

• Manufacturer Part Number: XC2V500-6FG456C
• Description: FPGA Virtex-II™ Family 500K Gates 6912 Cells 820MHz 0.15um/0.12um (CMOS) Technology 1.5V 456-Pin FBGA
• Manufacturer: Xilinx Inc

Specifications of XC2V500-6FG456C

• Package: 456FBGA
• Family Name: Virtex-II™
• Device Logic Units: 6912
• Device System Gates: 500000
• Number Of Registers: 6144
• Maximum Internal Frequency: 820 MHz
• Typical Operating Supply Voltage: 1.5 V
• Maximum Number Of User I/os: 264
• Ram Bits: 589824

Table 15: IOB Input Switching Characteristics Standard Adjustments (Continued)
DS031-3 (v3.5) November 5, 2007
Product Specification
Notes:
1. Input timing for LVTTL is measured at 1.4V. For other I/O standards, see
LVDCI, 3.3V, Half-Impedance
LVDCI, 2.5V, Half-Impedance
LVDCI, 1.8V, Half-Impedance
LVDCI, 1.5V, Half-Impedance
HSLVDCI (High-Speed Low-Voltage DCI), 1.5V
HSLVDCI, 1.8V
HSLVDCI, 2.5V
HSLVDCI, 3.3V
GTL (Gunning Transceiver Logic) with DCI
GTL Plus with DCI
HSTL (High-Speed Transceiver Logic), Class I, with DCI
HSTL, Class II, with DCI
HSTL, Class III, with DCI
HSTL, Class IV, with DCI
HSTL, Class I, 1.8V, with DCI
HSTL, Class II, 1.8V, with DCI
HSTL, Class III, 1.8V, with DCI
HSTL, Class IV, 1.8V, with DCI
SSTL (Stub Series Terminated Logic), Class I, 1.8V, with DCI
SSTL, Class II, 1.8V, with DCI
SSTL, Class I, 2.5V, with DCI
SSTL, Class II, 2.5V, with DCI
SSTL, Class I, 3.3V, with DCI
SSTL, Class II, 3.3V, with DCI
LVDS (Low-Voltage Differential Signaling), 2.5V, with DCI
LVDS, 3.3V, with DCI
LVDSEXT (LVDS Extended Mode), 2.5V, with DCI
LVDSEXT, 3.3V, with DCI
R
Description
www.xilinx.com
LVDSEXT_25_DCI
LVDSEXT_33_DCI
HSTL_IV_DCI_18
HSTL_III_DCI_18
HSTL_II_DCI_18
IOSTANDARD
HSTL_I_DCI_18
LVDCI_DV2_33
LVDCI_DV2_25
LVDCI_DV2_18
LVDCI_DV2_15
SSTL18_II_DCI
SSTL18_I_DCI
HSTL_IV_DCI
SSTL2_II_DCI
SSTL3_II_DCI
LVDS_25_DCI
LVDS_33_DCI
Virtex-II Platform FPGAs: DC and Switching Characteristics
HSTL_III_DCI
SSTL2_I_DCI
SSTL3_I_DCI
HSLVDCI_15
HSLVDCI_18
HSLVDCI_25
HSLVDCI_33
HSTL_II_DCI
HSTL_I_DCI
GTLP_DCI
Attribute
GTL_DCI
Table
18.
T
T
T
T
T
T
T
T
T
T
T
T
ILVDSEXT_25_DCI
ILVDSEXT_33_DCI
T
IHSTL_III_DCI_18
IHSTL_IV_DCI_18
T
T
T
T
T
T
T
IHSTL_II_DCI_18
T
T
T
T
T
IHSTL_I_DCI_18
Parameter
T
ILVDCI_DV2_33
ILVDCI_DV2_25
ILVDCI_DV2_18
ILVDCI_DV2_15
ISSTL18_II_DCI
ISSTL18_I_DCI
T
ISSTL2_II_DCI
ISSTL3_II_DCI
ILVDS_25_DCI
ILVDS_33_DCI
IHSTL_III_DCI
IHSTL_IV_DCI
ISSTL2_I_DCI
ISSTL3_I_DCI
IHSLVDCI_15
IHSLVDCI_18
IHSLVDCI_25
IHSLVDCI_33
IHSTL_II_DCI
T
IHSTL_I_DCI
Timing
IGTLP_DCI
IGTL_DCI
0.00
0.11
0.42
0.98
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.35
0.35
0.42
0.52
0.42
0.42
0.60
0.60
0.58
0.56
-6
Speed Grade
0.00
0.11
0.43
1.00
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.42
0.35
0.35
0.42
0.53
0.42
0.42
0.60
0.60
0.59
0.56
-5
0.00
0.12
0.49
1.14
0.48
0.48
0.48
0.48
0.48
0.48
0.48
0.48
0.48
0.48
0.48
0.48
0.48
0.48
0.40
0.40
0.48
0.60
0.48
0.48
0.69
0.69
0.79
0.65
-4
Module 3 of 4
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
12