XC2V500-6FG456C Xilinx Inc, XC2V500-6FG456C Datasheet - Page 79

• Manufacturer Part Number: XC2V500-6FG456C
• Description: FPGA Virtex-II™ Family 500K Gates 6912 Cells 820MHz 0.15um/0.12um (CMOS) Technology 1.5V 456-Pin FBGA
• Manufacturer: Xilinx Inc

Specifications of XC2V500-6FG456C

• Package: 456FBGA
• Family Name: Virtex-II™
• Device Logic Units: 6912
• Device System Gates: 500000
• Number Of Registers: 6144
• Maximum Internal Frequency: 820 MHz
• Typical Operating Supply Voltage: 1.5 V
• Maximum Number Of User I/os: 264
• Ram Bits: 589824

Virtex-II Pin-to-Pin Output Parameter Guidelines
All devices are 100% functionally tested. Listed below are representative values for typical pin locations and normal clock
loading. Values are expressed in nanoseconds unless otherwise noted.
Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, With DCM
Table 34: Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, With DCM
DS031-3 (v3.5) November 5, 2007
Product Specification
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
2. Output timing is measured at 50% V
LVTTL Global Clock Input to Output delay using
Output flip-flop, 12 mA, Fast Slew Rate, with
DCM.
For data output with different standards, adjust
the delays with the values shown in
Switching Characteristics Standard
Adjustments, page
Global Clock and OFF with DCM
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
R
Description
14.
IOB Output
CC
threshold with test setup shown in
T
Symbol
ICKOFDCM
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Virtex-II Platform FPGAs: DC and Switching Characteristics
XC2V1000
XC2V1500
XC2V2000
XC2V3000
XC2V4000
XC2V6000
XC2V8000
XC2V250
XC2V500
XC2V40
XC2V80
Device
Figure
1. For other I/O standards, see
1.10
1.10
1.10
1.10
1.10
1.10
1.10
1.19
1.19
1.64
-6
Speed Grade
1.28
1.28
1.28
1.28
1.28
1.28
1.28
1.38
1.38
1.88
1.88
-5
Table
1.48
1.48
1.48
1.48
1.48
1.48
1.48
1.59
1.59
2.17
2.17
-4
Module 3 of 4
19.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
31