XC3S1200E-4FG400I Xilinx Inc, XC3S1200E-4FG400I Datasheet - Page 156

• Manufacturer Part Number: XC3S1200E-4FG400I
• Description: FPGA Spartan®-3E Family 1.2M Gates 19512 Cells 572MHz 90nm (CMOS) Technology 1.2V 400-Pin FBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Er

Specifications of XC3S1200E-4FG400I

• Package: 400FBGA
• Family Name: Spartan®-3E
• Device Logic Cells: 19512
• Device Logic Units: 2168
• Device System Gates: 1200000
• Number Of Registers: 17344
• Maximum Internal Frequency: 572 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 304
• Ram Bits: 516096
• Number Of Logic Elements/cells: 19512
• Number Of Labs/clbs: 2168
• Total Ram Bits: 516096
• Number Of I /o: 304
• Number Of Gates: 1200000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

DC and Switching Characteristics
Serial Peripheral Interface (SPI) Configuration Timing
Table 118: Timing for Serial Peripheral Interface (SPI) Configuration Mode
156
(Open-Drain)
T
T
T
T
T
T
T
PROG_B
CCLK1
CCLKn
MINIT
INITM
CCO
DCC
CCD
Symbol
HSWAP
VS[2:0]
CSO_B
INIT_B
M[2:0]
CCLK
MOSI
(Input)
(Input)
(Input)
(Input)
(Input)
DIN
Shaded values indicate specifications on attached SPI Flash PROM.
Initial CCLK clock period
CCLK clock period after FPGA loads ConfigRate setting
Setup time on VS[2:0] and M[2:0] mode pins before the rising
edge of INIT_B
Hold time on VS[2:0] and M[2:0]mode pins after the rising edge of
INIT_B
MOSI output valid after CCLK edge
Setup time on DIN data input before CCLK edge
Hold time on DIN data input after CCLK edge
T
MINIT
Figure 77: Waveforms for Serial Peripheral Interface (SPI) Configuration
Pin initially pulled High by internal pull-up resistor if HSWAP input is Low.
Pin initially high-impedance (Hi-Z) if HSWAP input is High. External pull-up resistor required on CSO_B.
<1:1:1>
<0:0:1>
HSWAP must be stable before INIT_B goes High and constant throughout the configuration process.
T
INITM
T
CCLK1
Description
T
CSS
Command
Mode input pins M[2:0] and variant select input pins VS[2:0] are sampled when INIT_B
goes High. After this point, input values do not matter until DONE goes High, at which
point these pins become user-I/O pins.
(msb)
T
www.xilinx.com
CCO
T
DSU
T
MCCL1
Command
(msb-1)
T
MCCH1
T
DH
Minimum
Data
50
0
DS312-3 (v3.8) August 26, 2009
T
See
See
See
See
See
New ConfigRate active
T
CCLK1
MCCL n
Data
T
T
Maximum
V
Table 112
Table 112
Table 116
Table 116
Table 116
DCC
Product Specification
-
-
Data
T
CCD
ds312-3_06_110206
T
CCLK n
T
MCCH n
Units
ns
ns
Data
R