XC3S400-4FG456C Xilinx Inc, XC3S400-4FG456C Datasheet - Page 32

• Manufacturer Part Number: XC3S400-4FG456C
• Description: FPGA Spartan®-3 Family 400K Gates 8064 Cells 630MHz 90nm Technology 1.2V 456-Pin FBGA
• Manufacturer: Xilinx Inc

Specifications of XC3S400-4FG456C

• Package: 456FBGA
• Family Name: Spartan®-3
• Device Logic Units: 8064
• Device System Gates: 400000
• Maximum Internal Frequency: 630 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 264
• Ram Bits: 294912
• Case: BGA
• Dc: 07+

Spartan-3 FPGA Family: Functional Description
The
Delay-Locked Loop (DLL), the Digital Frequency Synthe-
sizer (DFS), the Phase Shifter (PS), and the Status Logic.
Each component has its associated signals, as shown in
Figure
32
54
DCM
17.
has
four
CLKFB
PSINCDEC
CLKIN
RST
PSCLK
CLKFB
CLKIN
PSEN
functional
RST
Figure 17: DCM Functional Blocks and Associated Signals
Figure 18: Simplified Functional Diagram of DLL
Delay
1
components:
DLL
Delay
2
Shifter
Status
DCM
Phase
Logic
Detection
Control
Phase
www.xilinx.com
the
DFS
Delay
n-1
Delay-Locked Loop (DLL)
The most basic function of the DLL component is to elimi-
nate clock skew. The main signal path of the DLL consists of
an input stage, followed by a series of discrete delay ele-
ments or taps, which in turn leads to an output stage. This
path together with logic for phase detection and control
forms a system complete with feedback as shown in
Figure
8
CLK90
CLK180
CLK270
CLK2X
CLK2X180
CLKDV
PSDONE
CLK0
CLKFX
CLKFX180
LOCKED
STATUS [7:0]
Delay
18.
n
Distribution
Delay
Clock
DS099-2_08_041103
DS099-2_07_040103
CLK0
CLK90
CLK180
CLK270
CLK2X
CLK2X180
CLKDV
LOCKED
DS099-2 (v2.5) December 4, 2009
Product Specification
R