XC3S400-4FGG320I Xilinx Inc, XC3S400-4FGG320I Datasheet - Page 13
![FPGA Spartan®-3 Family 400K Gates 8064 Cells 630MHz 90nm Technology 1.2V 320-Pin FBGA](/photos/6/72/67295/pk071-320_sml.jpg)
XC3S400-4FGG320I
Manufacturer Part Number
XC3S400-4FGG320I
Description
FPGA Spartan®-3 Family 400K Gates 8064 Cells 630MHz 90nm Technology 1.2V 320-Pin FBGA
Manufacturer
Xilinx Inc
Series
Spartan™-3r
Datasheet
1.XC3S50-4VQG100C.pdf
(217 pages)
Specifications of XC3S400-4FGG320I
Package
320FBGA
Family Name
Spartan®-3
Device Logic Units
8064
Device System Gates
400000
Maximum Internal Frequency
630 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
221
Ram Bits
294912
Number Of Logic Elements/cells
8064
Number Of Labs/clbs
896
Total Ram Bits
294912
Number Of I /o
221
Number Of Gates
400000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
320-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
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DS099-2 (v2.5) December 4, 2009
Product Specification
OTCLK1
OTCLK2
ICLK1
ICLK2
TCE
OCE
REV
ICE
IQ1
IQ2
T1
T2
SR
O1
O2
T
I
R
Note: All IOB signals originating from the FPGA's internal logic have an optional polarity inverter.
D
CE
CK
D
CE
CK
D
CE
CK
D
CE
CK
D
CE
CK
D
CE
CK
SR
SR
SR
SR
SR
SR
REV
REV
REV
REV
REV
REV
Q
Q
Q
Q
Q
Q
Figure 5: Simplified IOB Diagram
TFF1
TFF2
OFF1
OFF2
IFF1
IFF2
MUX
DDR
DDR
MUX
www.xilinx.com
Delay
Fixed
Delay
Fixed
Three-state Path
Output Path
Input Path
Spartan-3 FPGA Family: Functional Description
Program-
Output
mable
Driver
Single-ended Standards
LVCMOS, LVTTL, PCI
Differential Standards
using V REF
DCI
Pull-Up
Down
Pull-
Keeper
Latch
DS099-2_01_112905
ESD
ESD
V
Pin
I/O Pin
from
Adjacent
IOB
V
CCO
REF
I/O
Pin
13
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