XC3S400-4TQG144I Xilinx Inc, XC3S400-4TQG144I Datasheet - Page 133

FPGA Spartan®-3 Family 400K Gates 8064 Cells 630MHz 90nm Technology 1.2V 144-Pin TQFP

XC3S400-4TQG144I

Manufacturer Part Number
XC3S400-4TQG144I
Description
FPGA Spartan®-3 Family 400K Gates 8064 Cells 630MHz 90nm Technology 1.2V 144-Pin TQFP
Manufacturer
Xilinx Inc
Series
Spartan™-3r
Datasheet

Specifications of XC3S400-4TQG144I

Package
144TQFP
Family Name
Spartan®-3
Device Logic Units
8064
Device System Gates
400000
Maximum Internal Frequency
630 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
97
Ram Bits
294912
Number Of Logic Elements/cells
8064
Number Of Labs/clbs
896
Total Ram Bits
294912
Number Of I /o
97
Number Of Gates
400000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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User I/Os by Bank
Table 91
tributed between the eight I/O banks on the TQ144 pack-
age.
Table 91: User I/Os Per Bank in TQ144 Package
DS099-4 (v2.5) December 4, 2009
Product Specification
Package Edge
Bottom
Right
Left
Top
indicates how the available user-I/O pins are dis-
R
I/O Bank
0
1
2
3
4
5
6
7
Maximum
I/O
10
14
15
11
14
15
9
9
www.xilinx.com
I/O
10
11
10
11
5
4
0
0
DUAL
0
0
0
0
6
6
0
0
All Possible I/O Pins by Type
Spartan-3 FPGA Family: Pinout Descriptions
DCI
2
2
2
2
2
0
2
2
VREF
1
1
2
2
1
1
2
2
GCLK
2
2
0
0
2
2
0
0
133

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