XC5VLX30T-1FFG323I Xilinx Inc, XC5VLX30T-1FFG323I Datasheet - Page 45

• Manufacturer Part Number: XC5VLX30T-1FFG323I
• Description: FPGA Virtex®-5 Family 30720 Cells 65nm (CMOS) Technology 1V 323-Pin FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX30T-1FFG323I

• Package: 323FCBGA
• Family Name: Virtex®-5
• Device Logic Units: 30720
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 172
• Ram Bits: 1327104
• Number Of Logic Elements/cells: 30720
• Number Of Labs/clbs: 2400
• Total Ram Bits: 1327104
• Number Of I /o: 172
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 323-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 65: CLB Switching Characteristics (Cont’d)
DS202 (v5.3) May 5, 2010
Product Specification
Notes:
1.
2.
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
Sequential Delays
T
Setup and Hold Times of CLB Flip-Flops Before/After Clock CLK
T
T
T
T
T
Set/Reset
T
T
T
F
AXCY
CXB
CXD
DXD
OPCYA
OPCYB
OPCYC
OPCYD
BXCY
CXCY
DXCY
BYP
CINA
CINB
CINC
CIND
CKO
DICK
RCK
CECK
SRCK
CINCK
SRMIN
RQ
CEO
TOG
A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case”, but if a “0” is
listed, there is no positive hold time.
These items are of interest for Carry Chain applications.
/T
/T
/T
Symbol
/T
CKDI
CKCE
CKSR
CKCIN
CX inputs to CMUX output
CX inputs to DMUX output
DX inputs to DMUX output
An input to COUT output
Bn input to COUT output
Cn input to COUT output
Dn input to COUT output
AX input to COUT output
BX input to COUT output
CX input to COUT output
DX input to COUT output
CIN input to COUT output
CIN input to AMUX output
CIN input to BMUX output
CIN input to CMUX output
CIN input to DMUX output
Clock to AQ – DQ outputs
AX – DX input to CLK on A – D Flip Flops
DX input to CLK when used as REV
CE input to CLK on A – D Flip Flops
SR input to CLK on A – D Flip Flops
CIN input to CLK on A – D Flip Flops
SR input minimum pulse width
Delay from SR or REV input to AQ – DQ flip-flops
Delay from CE input to AQ – DQ flip-flops
Toggle frequency (for export control)
Description
www.xilinx.com
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
–0.04
–0.19
1412
0.33
0.37
0.38
0.43
0.39
0.33
0.30
0.36
0.26
0.20
0.20
0.09
0.24
0.27
0.29
0.31
0.35
0.36
0.19
0.37
0.18
0.41
0.14
0.14
0.90
0.74
0.46
-3
Speed Grade
–0.04
–0.19
1265
0.36
0.42
0.42
0.50
0.44
0.37
0.34
0.42
0.30
0.22
0.22
0.10
0.27
0.30
0.32
0.35
0.40
0.41
0.21
0.42
0.20
0.49
0.16
0.16
0.90
0.86
0.52
-2
–0.04
–0.19
1098
0.42
0.49
0.49
0.59
0.51
0.43
0.40
0.50
0.37
0.26
0.26
0.11
0.31
0.35
0.36
0.41
0.47
0.49
0.24
0.51
0.23
0.59
0.18
0.19
0.90
1.03
0.63
-1
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
Units
MHz
45