XC5VLX50T-1FF1136C Xilinx Inc, XC5VLX50T-1FF1136C Datasheet - Page 199

• Manufacturer Part Number: XC5VLX50T-1FF1136C
• Description: FPGA Virtex®-5 Family 46080 Cells 65nm (CMOS) Technology 1V 1136-Pin FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FF1136C

• Package: 1136FCBGA
• Family Name: Virtex®-5
• Device Logic Units: 46080
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 480
• Ram Bits: 2211840
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Total Ram Bits: 2211840
• Number Of I /o: 480
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1136-BBGA, FCBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: 122-1586 - BOARD EVAL FOR VIRTEX-5 ML555HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
carry multiplexer (MUXCY) can also be used to cascade function generators for
implementing wide logic functions.
Figure 5-24
X-Ref Target - Figure 5-24
The carry chains carry lookahead logic along with the function generators. There are ten
independent inputs (S inputs – S0 to S3, DI inputs – DI1 to DI4, CYINIT and CIN) and eight
independent outputs (O outputs – O0 to O3, and CO outputs – CO0 to CO3).
The S inputs are used for the “propagate” signals of the carry lookahead logic. The
“propagate” signals are sourced from the O6 output of a function generator. The DI inputs
are used for the “generate” signals of the carry lookahead logic. The “generate” signals are
sourced from either the O5 output of a function generator or the BYPASS input (AX, BX,
CX, or DX) of a slice. The former input is used to create a multiplier, while the latter is used
O6 From LUTD
O5 From LUTD
O6 From LUTC
O5 From LUTC
O6 From LUTB
O5 From LUTB
O6 From LUTA
O5 From LUTA
illustrates the carry chain with associated logic elements in a slice.
Figure 5-24: Fast Carry Logic Path and Associated Elements
DX
CX
BX
AX
www.xilinx.com
S3
DI3
S2
DI2
S1
DI1
S0
DI0
CYINIT
COUT (To Next Slice)
CIN (From Previous Slice)
0
MUXCY
MUXCY
MUXCY
MUXCY
1
CIN
Carry Chain Block
(CARRY4)
CO3
CO2
CO1
CO0
O3
O2
O1
O0
D Q
D Q
D Q
D Q
* Can be used if
unregistered/registered
outputs are free.
(Optional)
(Optional)
(Optional)
(Optional)
UG190_5_24_050506
CLB Overview
DMUX/DQ*
DMUX
DQ
CMUX/CQ*
CMUX
CQ
BMUX/BQ*
BMUX
BQ
AMUX/AQ*
AMUX
AQ
199