XC5VLX50T-1FF1136C Xilinx Inc, XC5VLX50T-1FF1136C Datasheet - Page 47

• Manufacturer Part Number: XC5VLX50T-1FF1136C
• Description: FPGA Virtex®-5 Family 46080 Cells 65nm (CMOS) Technology 1V 1136-Pin FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FF1136C

• Package: 1136FCBGA
• Family Name: Virtex®-5
• Device Logic Units: 46080
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 480
• Ram Bits: 2211840
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Total Ram Bits: 2211840
• Number Of I /o: 480
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1136-BBGA, FCBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: 122-1586 - BOARD EVAL FOR VIRTEX-5 ML555HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Clock Management Technology
Clock Management Summary
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
The Clock Management Tiles (CMTs) in the Virtex-5 family provide very flexible, high-
performance clocking. Each CMT contains two DCMs and one PLL.
simplified view of the center column resources including the CMT block, where the DCM
is located. Each CMT block contains two DCMs and one PLL.
X-Ref Target - Figure 2-1
www.xilinx.com
(Bottom Half DCMs/PLLs)
Figure 2-1: CMT Location
(Top Half DCMs/PLLs)
(Larger Devices Only)
(Larger Devices Only)
Config Blocks and
(Bottom Half)
(Bottom Half)
CMT Blocks
CMT Blocks
Config I/O
Config I/O
I/O Banks
(Top Half)
(Top Half)
I/O Banks
Clock I/O
Clock I/O
BUFGs
Center Column
Virtex-5 FPGA
UG190_c2_01_022609
Chapter 2
Figure 2-1
shows a
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