CY8C3866AXI-040 Cypress Semiconductor Corp, CY8C3866AXI-040 Datasheet - Page 83

• Manufacturer Part Number: CY8C3866AXI-040
• Description: PSOC 3 TQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: PSOC™ 3 CY8C38xxr

Specifications of CY8C3866AXI-040

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.71 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 67MHz
• Number Of I /o: 62
• Eeprom Size: 2K x 8
• Core Processor: 8051
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 64KB (64K x 8)
• Data Converters: A/D 2x20b, D/A 4x8b
• Oscillator Type: Internal
• Peripherals: CapSense, DMA, LCD, POR, PWM, WDT
• Connectivity: CAN, EBI/EMI, I²C, LIN, SPI, UART/USART, USB
• Core Size: 8-Bit
• Processor Series: CY8C38
• Core: 8051
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SPI, UART, USB
• Maximum Clock Frequency: 67 MHz
• Number Of Programmable I/os: 28 to 72
• Number Of Timers: 4
• Operating Supply Voltage: 0.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Controller Family/series: (8051) PSOC 3
• No. Of I/o's: 62
• Eeprom Memory Size: 2KB
• Ram Memory Size: 8KB
• Cpu Speed: 67MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.2.2 Delta-sigma ADC
Unless otherwise specified, operating conditions are:
Table 11-20. 20-bit Delta-sigma ADC DC Specifications
Document Number: 001-11729 Rev. *R
Ge
Gd
Vos
TCVos
PSRRb
CMRRb
INL20
DNL20
INL16
DNL16
INL12
DNL12
INL8
DNL8
Rin_Buff
Rin_ADC16 ADC input resistance
Rin_ADC12 ADC input resistance
Parameter
Notes
36. Based on device characterization (not production tested).
37. By using switched capacitors at the ADC input an effective input resistance is created. Holding the gain and number of bits constant, the resistance is proportional to
Operation in continuous sample mode
fclk = 3.072 MHz for resolution = 16 to 20 bits; fclk = 6.144 MHz for resolution = 8 to 15 bits
Reference = 1.024 V internal reference bypassed on P3.2 or P0.3
Unless otherwise specified, all charts and graphs show typical values
the inverse of the clock frequency. This value is calculated, not measured. For more information see the Technical Reference Manual.
Resolution
Number of channels, single ended
Number of channels, differential
Monotonic
Gain error
Gain drift
Input offset voltage
Temperature coefficient, input offset
voltage
Input voltage range, single ended
Input voltage range, differential unbuf-
fered
Input voltage range, differential,
buffered
Power supply rejection ratio, buffered
Common mode rejection ratio, buffered
Integral non linearity
Differential non linearity
Integral non linearity
Differential non linearity
Integral non linearity
Differential non linearity
Integral non linearity
Differential non linearity
ADC input resistance
[36]
[36]
Description
[36]
[36]
[36]
[36]
[36]
[36]
[36]
[36]
[36]
[36]
[36]
Differential pair is formed using a
pair of GPIOs.
Yes
Buffered, buffer gain = 1, Range =
±1.024 V, 16-bit mode, 25 °C
Buffered, buffer gain = 1, Range =
±1.024 V, 16-bit mode
Buffered, 16-bit mode, V
25 °C
Buffer gain = 1, 16-bit,
Range = ±1.024 V
Buffer gain = 1, 16-bit,
Range = ±1.024 V
Buffer gain = 1, 16 bit,
Range = ±1.024 V
Range = ±1.024 V, unbuffered
Range = ±1.024 V, unbuffered
Range = ±1.024 V, unbuffered
Range = ±1.024 V, unbuffered
Range = ±1.024 V, unbuffered
Range = ±1.024 V, unbuffered
Range = ±1.024 V, unbuffered
Range = ±1.024 V, unbuffered
Input buffer used
Input buffer bypassed, 16-bit, Range
= ±1.024 V
Input buffer bypassed, 12 bit, Range
= ±1.024 V
Conditions
DDA
= 2.7 V,
PSoC
V
V
V
Min
90
85
10
SSA
SSA
SSA
8
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
®
3: CY8C38 Family
148
74
Typ
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
[37]
[37]
V
GPIO/2
Data Sheet
No. of
No. of
DDA
GPIO
V
V
Max
±0.2
±0.1
±32
20
50
55
±1
±2
±1
±1
±1
±1
±1
DDA
DDA
–
–
–
–
–
–
Page 83 of 129
– 1
ppm/°C
µV/°C
Units
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
MΩ
bits
mV
kΩ
kΩ
dB
dB
%
–
–
–
V
V
V
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