LFE3-35EA-6FN484I LATTICE SEMICONDUCTOR, LFE3-35EA-6FN484I Datasheet - Page 27
LFE3-35EA-6FN484I
Manufacturer Part Number
LFE3-35EA-6FN484I
Description
FPGA LatticeECP3™ Family 33000 Cells 65nm Technology 1.2V 484-Pin FBGA
Manufacturer
LATTICE SEMICONDUCTOR
Datasheet
1.LFE3-150EA-7FN672C.pdf
(136 pages)
Specifications of LFE3-35EA-6FN484I
Package
484FBGA
Family Name
LatticeECP3Â
Device Logic Units
33000
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
295
Ram Bits
1358848
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Lattice Semiconductor
For further information, please refer to TN1182,
MULT DSP Element
This multiplier element implements a multiply with no addition or accumulator nodes. The two operands, AA and
AB, are multiplied and the result is available at the output. The user can enable the input/output and pipeline regis-
ters. Figure 2-26 shows the MULT sysDSP element.
Figure 2-26. MULT sysDSP Element
DSP Slice
Previous
IR = Input Register
PR = Pipeline Register
OR = Output Register
FR = Flag Register
Rounding
SRIB
SRIA
C_ALU
A_ALU
CIN
0
IR
C
IR
AA
MULTA
PR
OR
AMUX
A_ALU
IR
From FPGA Core
LatticeECP3 sysDSP Usage
AB
To FPGA Core
0
R = Logic (B, C)
R= A ± B ± C
2-24
OR
PR
IR
OPCODE
FR
0
=
=
B_ALU
BMUX
IR
ALU
BA
MULTB
LatticeECP3 Family Data Sheet
OR
PR
Guide.
IR
BB
IR
COUT
SROB
SROA
DSP Slice
Next
Architecture
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