LFE3-35EA-6FN484I LATTICE SEMICONDUCTOR, LFE3-35EA-6FN484I Datasheet - Page 99
LFE3-35EA-6FN484I
Manufacturer Part Number
LFE3-35EA-6FN484I
Description
FPGA LatticeECP3™ Family 33000 Cells 65nm Technology 1.2V 484-Pin FBGA
Manufacturer
LATTICE SEMICONDUCTOR
Datasheet
1.LFE3-150EA-7FN672C.pdf
(136 pages)
Specifications of LFE3-35EA-6FN484I
Package
484FBGA
Family Name
LatticeECP3Â
Device Logic Units
33000
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
295
Ram Bits
1358848
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE3-35EA-6FN484I
Manufacturer:
LATTICE
Quantity:
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Company:
Part Number:
LFE3-35EA-6FN484I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Part Number:
LFE3-35EA-6FN484I
Manufacturer:
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Quantity:
20 000
Lattice Semiconductor
XAUI/Serial Rapid I/O Type 3/CPRI LV E.30 Electrical and Timing
Characteristics
AC and DC Characteristics
Table 3-13. Transmit
Table 3-14. Receive and Jitter Tolerance
T
Z
J
J
1. Total jitter includes both deterministic jitter and random jitter.
2. Jitter values are measured with each CML output AC coupled into a 50-ohm impedance (100-ohm differential impedance).
3. Jitter and skew are specified between differential crossings of the 50% threshold of the reference signal.
4. Values are measured at 2.5 Gbps.
RL
RL
Z
J
J
J
J
T
1. Total jitter includes deterministic jitter, random jitter and sinusoidal jitter. The sinusoidal jitter tolerance mask is shown in Figure 3-18.
2. Jitter values are measured with each high-speed input AC coupled into a 50-ohm impedance.
3. Jitter and skew are specified between differential crossings of the 50% threshold of the reference signal.
4. Jitter tolerance parameters are characterized when Full Rx Equalization is enabled.
5. Values are measured at 2.5 Gbps.
TX_DDJ
TX_TJ
RX_DJ
RX_RJ
RX_SJ
RX_TJ
RF
TX_DIFF_DC
RX_DIFF
RX_EYE
RX_DIFF
RX_CM
Symbol
Symbol
1, 2, 3, 4
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
2, 3, 4
Differential return loss
Common mode return loss
Differential termination resistance
Deterministic jitter tolerance (peak-to-peak)
Random jitter tolerance (peak-to-peak)
Sinusoidal jitter tolerance (peak-to-peak)
Total jitter tolerance (peak-to-peak)
Receiver eye opening
Differential rise/fall time
Differential impedance
Output data deterministic jitter
Total output data jitter
Description
Description
Over Recommended Operating Conditions
Over Recommended Operating Conditions
3-46
Test Conditions
From 100 MHz
to 3.125 GHz
From 100 MHz
to 3.125 GHz
Test Conditions
20%-80%
DC and Switching Characteristics
LatticeECP3 Family Data Sheet
Min.
80
—
—
—
Min.
0.35
10
80
—
—
—
—
6
Typ.
100
80
—
—
Typ.
100
—
—
—
—
—
—
—
Max.
0.17
0.35
120
—
Max.
0.37
0.18
0.10
0.65
120
—
—
—
Ohms
Units
Ohms
Units
ps
UI
UI
dB
dB
UI
UI
UI
UI
UI