ISL55210IRTZ Intersil, ISL55210IRTZ Datasheet
ISL55210IRTZ
Specifications of ISL55210IRTZ
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ISL55210IRTZ Summary of contents
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... FIGURE 1. TYPICAL APPLICATION CIRCUIT CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 Intersil (and design trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. - 12-bit, 500MSPS ADC (<500mW) SNRFS = 64 ...
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... PART MARKING ISL55210IRTZ 5210 ISL55210IRTZ-T7 5210 ISL55210IRTZ-T7A 5210 ISL55210IRTZ-EVALZ Evaluation Board (Contact local sales) NOTES: 1. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb- free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020 ...
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... Thermal Resistance (Typical) +0.3V to GND-0. TQFN Package (Notes Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +125°C Maximum Continuous Operating Junction Temperature .+135°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Ambient Operating Temperature . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C = +3.3V Test Conditions 12dB open ...
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Electrical Specifications V differential input, differential output, input and output referenced to internal default V PARAMETER DC PERFORMANCE Open-loop Voltage Gain ( Input Offset Voltage Average Offset Voltage Drift Input Bias Current Average Bias Current Drift Input Offset ...
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Electrical Specifications V differential input, differential output, input and output referenced to internal default V PARAMETER POWER-DOWN Enable Voltage Threshold Disable Voltage Threshold Power-down Quiescent Current Input Bias Current Input Impedance Turn-on Time Delay Turn-off Time Delay NOTES: 6. Compliance ...
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Typical Performance Curves 27dB -12 -15 -18 TEST CIRCUIT # 200Ω, - 500mV DIFFERENTIAL O P-P - FREQUENCY (Hz) FIGURE 2. FREQUENCY RESPONSE vs GAIN ...
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Typical Performance Curves -60 TEST CIRCUIT # 200Ω L HD2 3V P-P -70 HD2 2V P-P -80 -90 HD2 1V P-P -100 -110 -120 20 FREQUENCY (MHz) FIGURE 8. HD2/HD3 vs V -60 TEST CIRCUIT #1 HD2, GAIN ...
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Typical Performance Curves 180 GROUP DELAY 27dB 165 150 135 120 105 GROUP DELAY 21dB GROUP DELAY 15dB 60 TEST CIRCUIT # 100 FREQUENCY (MHz) FIGURE 14. PHASE ...
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Typical Performance Curves 0.15 OUTPUT 0.10 0.05 INPUT 0 -0.05 -0.10 TEST CIRCUIT #1, 50MHz SQUARE WAVE INPUT -0. TIMEBASE (ns) FIGURE 20. SMALL SIGNAL STEP RESPONSE 100MHz OUTPUT ENABLED PD DISABLED 2µs/DIV FIGURE 22. ENABLE/DISABLE TIMES ...
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Typical Performance Curves 6 TEST CIRCUIT # MAXIMUM DIFFERENTIAL V OUTPUT USING DEFAULT INTERNALLY SET 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4.0 4.1 4.2 4.3 4.4 4.5 SUPPLY ...
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Most of the characterization curves start with Figure 28 then get different gains by changing the feedback resistor, R different input transformers where then the R to hold an input match, or vary the loading. For load tests below the ...
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For instance minimum noise configuration is not required, but it is desirable to increase the feedback resistors to reduce the added loading they present to the output stage, the R resistors can be scaled up to achieve the ...
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The V reported in Figure P-P P-P asymmetrically clipped maximum swing. Going 10% above this 3.7V target to 4.1V will be within the recommended operating range and give some tolerancing headroom that would also ...
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The maximum internal junction temperatures would occur at maximum supply voltage, +85°C maximum ambient operating, and where the QFN exposed pad is not tied to a conductive layer. Where the QFN must be mounted with an insulating layer to the ...
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AC coupled, higher frequency range interstage filter design. This design replaces the R resistors in Figure 34 with large t valued inductors and implements the filter just using shunt resistors at the end of the RLC filter (here, that ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. ...
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L1 +Vs + BEAD C1001 C1002 4.7µF 1.0µF GND Cterm1 R1 2.2pF R5 200Ω DNP ADT2- 0Ω 50Ω 1µF R0 DNP R7 0Ω R4 R23 50Ω R8 200Ω 0Ω R2 DNP Cterm2 2.2pF PD R22 50Ω ...
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Package Outline Drawing L16.3x3D 16 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 0, 3/10 3.00 6 PIN 1 INDEX AREA (4X) 0.15 TOP VIEW (2.80 TYP) ( 1.60) TYPICAL RECOMMENDED LAND PATTERN 18 ISL55210 4X 1.50 A 12X 0.50 ...