ATA5428-PLQW80 Atmel, ATA5428-PLQW80 Datasheet - Page 34
![RF Transceiver ASK/FSK Transceiver 434 and 868MHz](/photos/30/99/309912/qfn-48_sml.jpg)
ATA5428-PLQW80
Manufacturer Part Number
ATA5428-PLQW80
Description
RF Transceiver ASK/FSK Transceiver 434 and 868MHz
Manufacturer
Atmel
Datasheet
1.ATAB5428-8-WB.pdf
(100 pages)
Specifications of ATA5428-PLQW80
Wireless Frequency
226 KHz, 237 KHz
Interface Type
4-Wire SPI
Noise Figure
7 dB
Output Power
10 dBm
Operating Supply Voltage
2.4 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
QFN-48
Maximum Data Rate
20 Kbps
Minimum Operating Temperature
- 40 C
Modulation
ASK, FSK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Figure 5-3.
34
V
ATA5423/ATA5425/ATA5428/ATA5429
V
Thres_2
Thres_1
(Control Register 3)
DVCC_RESET
(Status Register)
Reset Timing
= 2.38V (typ)
VSOUT_EN
= 2.3V (typ)
N_RESET
LOW_Batt
VSOUT
VSOUT
(AVCC)
DVCC
The status bit Low_Batt is set to “1” if the voltage at pin VSOUT V
(typically 2.38V). Low_Batt is set to “0” if V
via the 4-wire serial interface or N_RESET is set to low.
If V
trol register 3 is “1”, a DVCC_RESET is also generated. If V
connected microcontroller by setting bit VSOUT_EN = 0, no DVCC_RESET is generated.
Note:
VSOUT
If VSOUT < V
is disabled and the transceiver is not programmable via the 4-wire serial interface.
drops below V
1.5V (typically)
V
SOUT
V
SOUT
> 2.3V and the XTO is running
Thres_1
> 2.38V and the XTO is running
Thres_1
(typically 2.3 V) the output of the pin CLK is low, the Microcontroller_Interface
(typically 2.3V), N_RESET is set to low. If bit VSOUT_EN in con-
VSOUT
exceeds V
Thres_2
VSOUT
and the status register is read
was already disabled by the
VSOUT
drops below V
4841D–WIRE–10/07
Thres_2
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