PI6C3991-5JE Pericom Semiconductor, PI6C3991-5JE Datasheet - Page 2

• Manufacturer Part Number: PI6C3991-5JE
• Description: Phase Locked Loops (PLL) Programmable Skew Zero Delay
• Manufacturer: Pericom Semiconductor
• Type: Zero Delay Programmable PLL Clock Bufferr

Specifications of PI6C3991-5JE

• Number Of Circuits: 1
• Output Frequency Range: 3.75 MHz to 80 MHz
• Supply Voltage (max): 3.63 V
• Supply Voltage (min): 2.97 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Package / Case: PLCC-32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2
1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2
Pin Descriptions
Table 1. Frequency Range Select and t
Notes:
1. For all three-state inputs, HIGH indicates a connection to V
2. The level to be set on FS is determined by the “normal” operating frequency (f
S
g i
F
4
1
2
3
H
open connection. Internal termination circuitry holds an unconnected input to V
(see Logic Block Diagram). Nominal frequency (f
their undivided modes (see Table 2). The frequency appearing at the REF and FB inputs will be f
to FB is undivided. The frequency of the REF and FB inputs will be f
multiplication by using a divided output as the FB input.
L
4
1
2
3
M
Q
Q
Q
S
Q
n
O
F
F
F
G I
F
T
V
V
G
(
R
l a
D I
, 0
, 0
, 0
, 0
, 0
, 0
, 0
, 0
, 1
F
E
W
F
C
C
N
E
H
) 2
B
S
S
C
C
N
F
2
3
4
2
3
4
1
1
D
T
N
Q
F
Q
F
F
F
Q
Q
Q
a
1
1
1
m
1
1
1
1
1
e
M
5 2
0 4
5 1
F
P
P
P
. n i
N
I
W
W
W
O
O /
O
O
O
O
I
I
I
I
I
I
I
I
M
R
R
R
(
M
O
O
O
O
r G
R
P
T
T
T
T
T
T
P
P
H
M
L
r h
r h
r h
r h
r h
r h
o
o
e
t u
t u
t u
t u
0 3
0 5
0 8
) z
u o
r e f
L
w
w
a
e e
e e
e e
e e
e e
e e
u p
u p
u p
u p
. x
r e
r e
d n
e f
n e
l -
e l -
e l -
e l -
e l -
l -
p t
p t
p t
p t
d e
v e
v e
u s
u s
e c
e v
e v
e v
e v
r i a
r i a
r i a
r i a
a b
l e
l e
p p
p p
t
r f
f l
f l
f l
f l
U
k c
e r f
e s
. 1
. 2
. 3
. 4
y l
y l
q e
n u
n u
n u
n u
=
w
e l
u q
f
f
e u
S
S
S
S
e h
i t c
i t c
i t c
i t c
n i
r o
r o
f
. t c
NOM
e e
e e
e e
e e
u p
c n
n e
n o
n o
n o
n o
4 4
e r
6 2
6 1
o
n i
S
i y
( t
y c
T
T
T
T
t u
r e t
1
N
s
s
s
s
e e
b a
b a
b a
b a
u p
l e
l e
l e
l e
y t
p n
× N
=
r
a n
n a
c e
c e
c e
c e
e l
e l
e l
e l
i p
e t
d t
. t u
c l
a c
i t
i t
i t
i t
t s
e g
2
2
2
2
i r
U
c r i
p n
p n
p n
p n
T
y l l
m
e v
e s
i h
Calculation
o
t i u
w
t u
t u
t u
t u
F
s r
c
i s
e l
e d
A
i h
e r
n o
f s
f s
f s
f s
y r
t c
p n
p
h c
q
NOM
e n
r o
r o
r o
r o
s .
e s
p
( .
t u
o r
2 2
8 3
2 6
t c
i t c
t
e e
o
o
o
o
M
U
u s
i x
d e
t u
t u
t u
t u
n o
7 .
5 .
5 .
=
) always appears at 1Q0 and the other outputs when they are operated in
T
m
H
p p
u p
u p
u p
u p
b a
1
o t
a
) z
n u
0 .
p t
p t
p t
p t
e i l
e t
e l
CC
o
e d
s n
t a
t s
r i a
r i a
r i a
r i a
e n
(1)
. 1
t r
, LOW indicates a connection to GND, and MID indicates an
e h
o
1
2
3
4
e h
2
t f
e r f
1 (
2 (
3 (
4 (
e h
Table 2. Programmable Skew Configurations
b
Q
Q
Q
Q
u q
o l
1
, 0
, 0
, 0
, 0
3
i e
k c
n e
F
NOM
F
H
H
H
L
L
L
h g
D
M
M
M
, 1
, 1
1
2
3
4
y c
O
O
O
G I
G I
G I
F
i d
e
Q
Q
Q
Q
o t
D I
D I
D I
u
W
W
W
2
g a
4
c s
H
H
H
a
1
1
1
1
3.3V High-Speed, Low-Voltage Programmable
n
F
/2 or f
F
t u
d n
. )
. )
. )
. )
t c
a r
i r
, 1
1
u p
t p
S
S
S
S
o i
m
i t
NOM
e e
e e
e e
e e
) s t
o i
n
i m
e d
NOM
n
S
CC
g n
T
T
T
T
1
c s
3
l e
b a
b a
b a
b a
F
F
) and Time Unit Generator
H
H
H
L
L
L
/2.
p i r
c e
a
M
M
M
, 0
, 0
e l
e l
e l
e l
a g
O
O
O
G I
G I
G I
/4 when the part is configured for a frequency
s t
o i t
D I
D I
D I
2
W
W
W
n i
. 2
. 2
. 2
. 2
4
H
H
H
F
F
s n
t s
, 0
0
Skew Clock Buffer - SuperClock
w
i h
h c
1
2
Q
l l a
Q
+
+
+
+
, 0
–
–
–
–
, 0
t 0
t 4
t 3
t 2
t 1
t 1
t 2
t 3
t 4
u f
NOM
U
1
2
c n
U
U
U
U
U
U
U
U
Q
Q
o i t
, 1
1
when the output connected
a n
O
u
v l
p t
D
D
3
i r a
t u
i v i
i v i
Q
i t a
–
–
–
+
+
+
, 0
e d
e d
t 0
F
t 6
t 4
t 2
t 2
t 4
t 6
n o
u
U
3
U
U
U
U
U
U
n
y b
y b
Q
t c
s i
1
2
4
o i
m
PS8450D
s n
a e
PI6C3991
D
u s
4
I
Q
i v i
e r
(1)
v n
+
+
+
–
–
–
, 0
e d
t 0
. d
t 6
t 4
t 2
t 2
t 4
t 6
t r e
U
11/12/08
4
U
U
U
U
U
U
y b
d e
Q
1
2
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