CY2308SC-1HT Cypress Semiconductor Corp, CY2308SC-1HT Datasheet

Phase Locked Loops (PLL) 3. 3V ZDB Internal Feedck

CY2308SC-1HT

Manufacturer Part Number

CY2308SC-1HT

Description

Phase Locked Loops (PLL) 3. 3V ZDB Internal Feedck

Manufacturer

Cypress Semiconductor Corp

Type

Zero Delay PLL Clock Bufferr

Datasheet

1.CY2308SC-1HT.pdf (15 pages)

Specifications of CY2308SC-1HT

Number Of Circuits

Output Frequency Range

10 MHz to 133.3 MHz

Supply Voltage (max)

3.6 V

Supply Voltage (min)

3 V

Maximum Operating Temperature

+ 70 C

Minimum Operating Temperature

0 C

Mounting Style

SMD/SMT

Operating Supply Voltage

3.3 V

Package / Case

SOIC-16

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

CY2308SC-1HT

Manufacturer:

Quantity:

2 300

Company:

Meier Automation Equipment Co., Limited

Part Number:

CY2308SC-1HT

Manufacturer:

CYPRESS/赛普拉斯

Quantity:

20 000

Current page: 1 of 15
Download datasheet (396Kb)

Cypress Semiconductor Corporation

Document Number: 38-07146 Rev. *E

Features

■

Functional Description

The CY2308 is a 3.3V Zero Delay Buffer designed to distribute

high speed clocks in PC, workstation, datacom, telecom, and

other high performance applications.

The part has an on-chip PLL that locks to an input clock

presented on the REF pin. The PLL feedback is driven into the

FBK pin and obtained from one of the outputs. The

input-to-output skew is less than 350 ps and output-to-output

skew is less than 200 ps.

The CY2308 has two banks of four outputs each that is

controlled by the Select inputs as shown in the table

Logic Block Diagram

Zero input-output propagation delay, adjustable by

capacitive load on FBK input

Multiple configurations, see

tions”

Multiple low skew outputs

Two banks of four outputs, three-stateable by two select

inputs

10 MHz to 133 MHz operating range

75 ps typical cycle-to-cycle jitter (15 pF, 66 MHz)

Space saving 16-pin 150 mil SOIC package or 16-pin TSSOP

3.3V operation

Industrial Temperature available

on page 3

REF

“Available CY2308 Configura-

Extra Divider (–5H)

Extra Divider (–3, –4)

•

Extra Divider (–2, –3)

198 Champion Court

Select Input

Decoding

PLL

“Select

MUX

Input Decoding”

required, Bank B is three-stated. The input clock is directly

applied to the output for chip and system testing purposes by

the select inputs.

The CY2308 PLL enters a power down state when there are

no rising edges on the REF input. In this mode, all outputs are

three-stated and the PLL is turned off resulting in less than

50 μA of current draw. The PLL shuts down in two additional

cases as shown in the table

page 2.

Multiple CY2308 devices accept the same input clock and

distribute it in a system. In this case, the skew between the

outputs of two devices is less than 700 ps.

The CY2308 is available in five different configurations as

shown in the table

page 3. The CY2308–1 is the base part where the output

frequencies equal the reference if there is no counter in the

feedback path. The CY2308–1H is the high drive version of the

–1 and rise and fall times on this device are much faster.

The CY2308–2 enables the user to obtain 2X and 1X

frequencies on each output bank. The exact configuration and

output frequencies depend on the output that drives the

feedback pin. The CY2308–3 enables the user to obtain 4X

and 2X frequencies on the outputs.

The CY2308–4 enables the user to obtain 2X clocks on all

outputs. Thus, the part is extremely versatile and is used in a

variety of applications.

The CY2308–5H is a high drive version with REF/2 on both

banks.

•

San Jose

3.3V Zero Delay Buffer

on page

“Available CY2308 Configurations”

CA 95134-1709

FBK

CLKA1

CLKA2

CLKA3

CLKA4

CLKB1

CLKB2

CLKB3

CLKB4

2”.

If all output clocks are not

“Select Input Decoding”

Revised August 03, 2007

•

408-943-2600

CY2308

[+] Feedback

Related parts for CY2308SC-1HT

CY2308SC-1HT Summary of contents

Page 1

... Logic Block Diagram REF /2 Extra Divider (–5H Cypress Semiconductor Corporation Document Number: 38-07146 Rev. *E Input Decoding” required, Bank B is three-stated. The input clock is directly applied to the output for chip and system testing purposes by the select inputs. The CY2308 PLL enters a power down state when there are no rising edges on the REF input ...

Page 2

Pinouts Table 1. Pin Definitions - 16 Pin SOIC Pin Signal [1] 1 REF [2] 2 CLKA1 [2] 3 CLKA2 GND [2] 6 CLKB1 [2] 7 CLKB2 [ [ [2] 10 CLKB3 ...

Page 3

Available CY2308 Configurations Device Feedback From CY2308–1 Bank A or Bank B CY2308–1H Bank A or Bank B CY2308–2 Bank A CY2308–2 Bank B CY2308–3 Bank A CY2308–3 Bank B CY2308–4 Bank A or Bank B CY2308–5H Bank A or ...

Page 4

Maximum Ratings Supply Voltage to Ground Potential................–0.5V to +7.0V DC Input Voltage (Except Ref) .............. –0. Input Voltage REF ........................................... –0 Operating Conditions for Commercial Temperature Devices Parameter V Supply Voltage DD T Operating Temperature ...

Page 5

Switching Characteristics for Commercial Temperature Devices Parameter Name t Output Frequency 1 t Output Frequency 1 t Output Frequency 1 ÷ t [7] Duty Cycle = (–1, –2, –3, –4, –1H, –5H) ÷ t [7] Duty Cycle ...

Page 6

Operating Conditions for Industrial Temperature Devices Parameter V Supply Voltage DD T Operating Temperature (Ambient Temperature Load Capacitance, below 100 MHz L Load Capacitance, from 100 MHz to 133 MHz [6] C Input Capacitance IN t Power-up time ...

Page 7

Switching Characteristics for Industrial Temperature Devices Parameter Name t Output Frequency 1 t Output Frequency 1 t Output Frequency 1 ÷ t [7] Duty Cycle = (–1, –2, –3, –4, –1H, –5H) [7] ÷ t Duty Cycle ...

Page 8

Switching Waveforms 1.4V 2.0V OUTPUT 0. 1.4V OUTPUT OUTPUT INPUT FBK t 6 FBK, Device 1 FBK, Device 2 t Document Number: 38-07146 Rev. *E Figure 2. Duty Cycle Timing ...

Page 9

Typical Duty Cycle [10] and I DD Duty Cycle Vs VDD (for 30 pF Loads over Frequency - 3.3V, 25C 3.1 3.2 3.3 3.4 3.5 VDD (V) Duty ...

Page 10

Typical Duty Cycle [10] and I DD Duty Cycle Vs VDD (for 30 pF Loads over Frequency - 3.3V, 25C 3.1 3.2 3.3 3.4 3.5 VDD (V) Duty ...

Page 11

Test Circuits Test Circuit 0.1 μF Outputs V DD 0.1 μF GND GND Test Circuit for all parameters except t Document Number: 38-07146 Rev. *E Test Circuit 0.1 μF CLK OUT C LOAD V ...

Page 12

... SOIC CY2308SI–2T 16-pin 150 mil SOIC - Tape and Reel CY2308SC–3 16-pin 150 mil SOIC CY2308SC–3T 16-pin 150 mil SOIC - Tape and Reel CY2308SC–4 16-pin 150 mil SOIC CY2308SC–4T 16-pin 150 mil SOIC - Tape and Reel CY2308SI– ...

Page 13

Ordering Information (continued) Ordering Code CY2308SXI–3 16-pin 150 mil SOIC CY2308SXI–3T 16-pin 150 mil SOIC -Tape and Reel CY2308SXC–4 16-pin 150 mil SOIC CY2308SXC–4T 16-pin 150 mil SOIC - Tape and Reel CY2308SXI–4 16-pin 150 mil SOIC CY2308SXI–4T 16-pin 150 ...

Page 14

Package Drawings and Dimensions 16 Lead (150 Mil) SOIC 8 9 0.386[9.804] 0.393[9.982] 0.050[1.270] BSC 0.0138[0.350] 0.0192[0.487] 1 4.30[0.169] 4.50[0.177] 16 0.65[0.025] BSC. 0.19[0.007] 0.30[0.012] 0.05[0.002] 0.85[0.033] 0.15[0.006] 0.95[0.037] 4.90[0.193] 5.10[0.200] Document Number: 38-07146 Rev. *E 16-Pin (150 Mil) SOIC ...

Page 15

... Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement ...

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