ATR2733-PLQW Atmel, ATR2733-PLQW Datasheet - Page 7

• Manufacturer Part Number: ATR2733-PLQW
• Description: RF Wireless Misc COM.RADIO-Frontend; VHF Band
• Manufacturer: Atmel

Specifications of ATR2733-PLQW

• Package / Case: QFN-48
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.9
3.10
3.11
3.12
3.13
4926BS–DAB–05/06
Fast Fractional PLL
Reference Oscillator
Reference Divider
Main Divider
Phase Comparator and Charge Pump
The frequency of the VHF VCO is locked to a reference frequency by an on-chip fractional-N
PLL circuit which guarantees superior phase-noise performance. The reference frequencies for
the PLL block are generated by an on-chip oscillator.
The VCOs are fully integrated, which simplifies the design of the device and reduces the bill of
materials of the application.
The down-converting to an IF frequency of 38.912 MHz for VHF signal is done by an additional
on-chip VCO using an internal fractional-N PLL.
Due to the digital tuning option of the reference frequency, the ATR2733 is able to support the
single reference clock design if the baseband can support such a feature (as the ATR2740
does).
An on-chip crystal oscillator generates the reference signal which is fed to the reference divider.
By applying a crystal to the pins XTALA and XTALB, this oscillator generates a highly stable ref-
erence signal.
Furthermore, the frequency of this reference oscillator can be digitally tuned via the SPI bus bits
XOTi (i = 11, ..., 0) with a 12-bit step size.
Starting from a minimum value, the scaling factor of the 6-bit reference divider is arbitrarily
programmable by means of the SPI bus bits Ri (i = 5, ..., 0).
A programmable divider (dividing by 8 to 128) then outputs 64 kHz, which is a useful reference
frequency for the VHF PLL.
Together with the fractional-N PLL, a step size of 16 kHz for the frequency setting of the VHF LO
is ensured.
The main divider consists of a fully programmable 13-bit divider which defines a division ratio N.
The applied division ratio is either N or N + 1, as specified by a special control unit. On average,
the scaling factors SF = N + k / 4 can be selected where k = 0, 1, 2, or 3.
The tri-state phase detector cause the charge pump to source or sink currents at the output pins
PFDOUTV (for VHF) depending on the phase relation of its input signals, which are provided by
the reference and the main dividers, respectively.
Internal lock detectors check if the phase difference of the phase detector’s input signals are
smaller than approximately 5 ns in 16 subsequent comparisons (in the case of VHF). These
numbers ensure a less than 4-kHz offset from the final frequency when lock-detect bits VHF-
PLLLD (SPI bus, output MISO) are set.
ATR2733 [Preliminary]
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