PI6C3Q993-5QEX Pericom Semiconductor, PI6C3Q993-5QEX Datasheet - Page 8

• Manufacturer Part Number: PI6C3Q993-5QEX
• Description: Phase Locked Loops (PLL) Programmable Skew Zero Delay
• Manufacturer: Pericom Semiconductor
• Type: Programmable PLL Clock Driverr

Specifications of PI6C3Q993-5QEX

• Number Of Circuits: 1
• Maximum Input Frequency: 85 MHz
• Minimum Input Frequency: 3.75 MHz
• Output Frequency Range: 15 MHz to 85 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Package / Case: QSOP-28
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2
1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2
Notes:
V
Skew:
t
t
t
t
t
t
t
t
Notes:
22. Input timing requirements are guaranteed by design. Where pulse width implied by D
SKEW0
DEV
ODCV
LOCK
ORISE
SKEWPR
PWH
PWL
CCQ
t
:
PWC
/PE: The AC timing diagram above applies to V
:
:
& t
:
09-0003
S
: The skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0t
limit applies.
t
OFALL
y
t
R
of REF, divided outputs change on the negative edge of REF, and the positive edges of the divide-by-2 and the divide-by-4 signals
align.
The time between the earliest and the latest output transition among all outputs for which the same t
all are loaded with 20pF and terminated with 75ohms to V
The skew between outputs when they are selected for 0t U.
The output-to-output skew between any two devices operating under the same conditions (V
air flow, etc.)
The deviation of the output from a 50% duty cycle. Output pulse width variations are included in t
The time that is required before synchronization is achieved. This specification is valid only after V
operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until t
specified limits.
is measured at 2.0V.
are measured between 0.8V and 2.0V.
P
D
is measured at 0.8V.
m
t ,
W
H
b
C
F
REF Divided by 2
REF Divided by 4
l o
Inverted Q
Other Q
M
n I
I
REF
p n
u p
FB
x a
Q
t u
c t
m i
t
u d
PD
u
o l
m
y t
k c
i
p n
c
u p
c y
t u
e l
s l
Table 10. Input Timing Requirements
i r
, e
e s
t
SKEW1,3,4
t
I H
REF
t
t
t
SKEW0, 1
SKEWPR
SKEW3,4
a
Figure 2. AC Timing Diagram
G
t
d n
RPWH
CCQ
H
D
a f
r o
/PE=V
e
t l l
c s
L
m i
O
i r
e
t
t p
W
CC
ODCV
, s
3.3V Programmable Skew PLL Clock Driver SuperClock
o i
. For V
0
n
CC
8 .
t
SKEW3,4
8
V
/2.
t
SKEW2
t
RPWL
CCQ
t
o t
ODCV
t
2
t
SKEW0, 1
SKEWPR
/PE=GND, the negative edge of FB aligns with the negative edge
0 .
V
(22)
H
t
is less than t
SKEW2
U
CC
M
.
0 1
, ambient temperature,
3
i
. n
t
t
SKEW3,4
SKEW2,4
SKEW2
CC
PI6C3Q991, PI6C3Q993
U
PWC
delay has been selected when
is stable and within normal
limit,
and t
M
t
JR
0 1
0 9
a
SKEW4
. x
PS8449H
PD
is within
specifications.
U
s n
n
s n
%
V /
s t i
10/27/09
®