8531AY-01 Integrated Device Technology (Idt), 8531AY-01 Datasheet - Page 12

• Manufacturer Part Number: 8531AY-01
• Description: Clock Driver 2-IN LVPECL 32-Pin TQFP Tray
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 8531AY-01

• Package: 32TQFP
• Configuration: 1 x 2:1
• Input Signal Type: CML|GTL|HCSL|LVCMOS|LVDS|LVHSTL|LVPECL|LVTTL|SSTL
• Maximum Output Frequency: 500 MHz
• Operating Supply Voltage: 3.3 V

This section provides information on power dissipation and junction temperature for the ICS8531-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8531-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
T
IDT
ABLE
ICS8531-01
LOW SKEW, 1-TO-9, DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
™
•
•
/ ICS
6. T
Power (core)
Power (outputs)
If all outputs are loaded, the total power is 9 * 30mW = 270mW
Total Power
The equation for Tj is as follows: Tj = θ
Tj = Junction Temperature
θ
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
70°C + 0.547W * 42.1°C/W = 93°C. This is well below the limit of 125°C.
™
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
JA
A
1-TO-9, 3.3V LVPECL FANOUT BUFFER
= Ambient Temperature
HERMAL
= junction-to-Ambient Thermal Resistance
R
MAX
_MAX
ESISTANCE
= V
MAX
(3.465V, with all outputs switching) = 277.2mW + 270mW = 547.2mW
= 30mW/Loaded Output pair
CC_MAX
θ θ θ θ θ
* I
JA
EE_MAX
FOR
θ θ θ θ θ
JA
= 3.465V * 80mA = 277.2mW
32-
by Velocity (Linear Feet per Minute)
CC
PIN
= 3.3V + 5% = 3.465V, which gives worst case results.
P
LQFP F
OWER
JA
* Pd_total + T
ORCED
C
ONSIDERATIONS
C
A
ONVECTION
12
67.8°C/W
47.9°C/W
0
TM
devices is 125°C.
55.9°C/W
42.1°C/W
200
ICS8531AY-01 REV. F APRIL 11, 2007
JA
must be used. Assuming a
50.1°C/W
39.4°C/W
500