SCANSTAEVK/NOPB National Semiconductor, SCANSTAEVK/NOPB Datasheet - Page 19

• Manufacturer Part Number: SCANSTAEVK/NOPB
• Manufacturer: National Semiconductor

Specifications of SCANSTAEVK/NOPB

• Lead Free Status / RoHS Status: Compliant

Special Features
TRANSPARENT MODE
While this mode is activated, the selected LSP n ports will
follow the backplane ports. TRST
TRST
buffered version of TMS
and TDO
are asserted when the state machine is in either the Shift-DR
or Shift-IR states. The unselected LSPs are placed in the
PARKTLR state, and their clocks are gated after 512 TCK
clock cycles.
Transparent Mode is controlled by 8 new instructions,
TRANSPARENT0 through TRANSPARENT7. Transparent
Mode overrides any other active mode. When one of the
transparent mode instruction is shifted into the instruction
register and the tap controller goes through the UPDATE-IR
state, TRST
force the targets connected to the LSP
RTI state. Then as the STA111 state machine goes into the
RTI state, all of the LSP
signals. This is identical to the method that is typically used
to unpark an LSP. The STA111 will remain in this mode until
a TRST
the Transparent Mode, the STA111 will not be able to be
reset by a 5 TMS high reset.
The sequence of operations to use Transparent Mode on an
LSP are as follows (example uses LSP
1. IR-Scan the STA111 address into the instruction register
2. IR-Scan the TRANSPARENT0 instruction to enable
NOTE: Transparent Mode will persist until the STA111 is
reset using TRST
instructions will not work in this mode.
BIST SUPPORT
The sequence of instructions to run BIST testing on a parked
SCANSTA111 port is as follows:
1. Pre-load the Boundary register of the device under test if
2. Issue the CNTRSEL instruction and initialize (load) the
3. Issue the CNTRON instruction to the ’STA111, to enable
4. Shift the PARKRTI instruction into the ’STA111 instruc-
5. Issue the CNTRSEL instruction to the ’STA111.
(address a STA111).
Transparent Mode on LSP
abled when the TAP enters the RTI state at the end of
this shift operation (TRST
come buffered versions of TRST
TCK
needed.
TCK counter to 00000000 Hex. Note that the TCK
counter is initialized to 00000000 Hex upon Test-Logic-
Reset, so this step may not be necessary.
the TCK counter.
tion register and BIST instruction into the instruction
register of the device under test. With the counter on (at
terminal count) and the LSP parked, the local TCK is
gated.
B
, TCK
B
B
B
is asserted or a power cycle forces a reset. Once in
and TDO
is a buffered version of TDI
n
n
will go high, and TMS
is a buffered version of TCK
B
B
. The GOTOWAIT and SOFTRESET
becomes a buffered version of TDI
B
n
, TDO
signals will follow the back-plane
0
n
, TDO
0
is a buffered version of TDI
. Transparent Mode is en-
n
is a buffered version of
n
0
n
, TMS
. TRIST
n
will go low. This will
B
0
, TDI
ports to go into the
):
0
and TCK
B
B
B
, TMS
, TMS
and TRIST
n
B
0
is a
and
be-
0
).
B
B
n
19
6. Load the TCK counter (Shift the 32-bit value represent-
7. Bit 7 of Mode Register
8. Execute the CNTROFF instruction.
9. Unpark the LSP and scan out the result of the BIST
RESET
Reset operations can be performed at three levels. The
highest level resets all ’STA111 registers and all of the local
scan chains of selected and unselected ’STA111s. This Level
1 reset is performed whenever the ’STA111 TAP Controller
enters the Test-Logic-Reset state. Test-Logic-Reset can be
entered synchronously by forcing TMS
(5) TCK
pin. A Level 1 reset forces all ’STA111s into the Wait-For-
Address state, parks all local scan chains in the Test-Logic-
Reset state, and initializes all ’STA111 registers.
The SOFTRESET instruction is provided to perform a Level
2 reset of all LSP’s of selected ’STA111s. SOFTRESET
forces all TMS
TAP Controllers in the Test-Logic-Reset state within five (5)
TCK
The third level of reset is the resetting of individual local
ports. An individual LSP can be reset by parking the port in
the Test-Logic-Reset state via the PARKTLR instruction. To
reset an individual LSP that is parked in one of the other
parked states, the LSP must first be unparked via the UN-
PARK instruction.
PORT SYNCHRONIZATION
When a LSP is not being accessed, it is placed in one of the
four TAP Controller states: Test-Logic-Reset, Run-Test/Idle,
Pause-DR, or Pause-IR. The ’STA111 is able to park a local
chain by controlling the local Test Mode Select outputs
(TMS
the Test-Logic-Reset state, and forced low for parking in
Run-Test/Idle, Pause-IR, or Pause-DR states. Local chain
access is achieved by issuing the UNPARK instruction. The
LSPs do not become unparked until the ’STA111 TAP Con-
troller is sequenced through a specified synchronization
state. Synchronization occurs in the Run-Test/Idle state for
LSPs parked in Test-Logic-Reset or Run-Test/Idle; and in the
Pause-DR or Pause-IR state for ports parked in Pause-DR
or Pause-IR, respectively.
Figure 11 and Figure 12 show the waveforms for synchroni-
zation of a local chain that was parked in the Test-Logic-
Reset state. Once the UNPARK instruction is received in the
instruction register, the LSPC forces TMS
edge of TCK
ing the number of TCK
BIST operation into the TCK counter register). The Self
test will begin on the rising edge of TCK
Update-DR TAP controller state.
status of the TCK counter, (MODESEL instruction fol-
lowed by a Shift-DR). Bit 7 logic 0 means the counter
has not reached terminal count, logic 1 means that the
counter has reached terminal count and the BIST opera-
tion has completed.
operation
B
(0-2)
cycles.
B
) (see Figure 4). TMS
pulses, or asynchronously by asserting the TRST
B
n
.
signals high, placing the corresponding local
n
0
cycles needed to execute the
can be scanned to check the
n
is forced high for parking in
B
high for at least five
n
low on the falling
B
following the
www.national.com
B