MPC8536DS Freescale, MPC8536DS Datasheet - Page 110

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MPC8536DS

Manufacturer Part Number
MPC8536DS
Description
Manufacturer
Freescale
Datasheet

Specifications of MPC8536DS

Lead Free Status / RoHS Status
Compliant
Thermal
2.23.6
2.23.6.1
Table 78
comparison to the memory bus clock speed.
2.23.6.2
Section 4.4.3.8 “SerDes1 I/O Port Selection” and Section 4.4.3.9 “SerDes2 I/O Port Selection” of the MPC8536E
PowerQUICC™ III Integrated Host Processor Family Reference Manual, describes various high-speed interface configuration
options. Note that the CCB clock frequency must be considered for proper operation of such interfaces as described below.
For proper PCI Express operation, the CCB clock frequency must be equal or greater than:
See Section 18.1.3.2, “Link Width,” of the MPC8536E PowerQUICC™ III Integrated Host Processor Family Reference
Manual, for PCI Express interface width details. Note that the “PCI Express link width” in the above equation refers to the
negotiated link width as the result of PCI Express link training, which may or may not be the same as the link width POR
selection.
2.24
This section describes the thermal specifications of the MPC8536E.
110
shows the expected frequency values for the platform frequency when using a CCB clock to SYSCLK ratio in
Thermal
Frequency Options
SYSCLK to Platform Frequency Options
Minimum Platform Frequency Requirements for High-speed Interfaces
Table 78. Frequency Options of SYSCLK with Respect to Memory Bus Speeds
SYSCLK Ratio
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
CCB to
10
12
16
3
4
5
6
8
33.33
333
400
533
527 MHz
----------------------------------------------------------------------------------------------
41.66
333
417
500
×
Platform /CCB Frequency (MHz)
(
PCI Express link width
66.66
333
400
533
8
SYSCLK (MHz)
333
415
500
83
100
400
500
)
111
333
444
Freescale Semiconductor
133.33
400
533