MPC8536DS Freescale, MPC8536DS Datasheet - Page 71

• Manufacturer Part Number: MPC8536DS
• Manufacturer: Freescale

Specifications of MPC8536DS

• Lead Free Status / RoHS Status: Compliant

Figure 39
Freescale Semiconductor
to
Figure 42
UPM Mode Input Signal:
Output (Address) Signal:
LA[27:31]/LBCTL/LOE
Output (Data) Signals:
In PLL bypass mode, some signals are launched and captured on the opposite edge of
LCLK[n] to that used in PLL Enable Mode. In this mode, output signals are launched at the
falling edge of the LCLK[n] and inputs signals are captured at the rising edge of LCLK[n]
with the exception of LGTA/LUPWAIT (which is captured at the falling edge of the
LCLK[n]).
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
LAD[0:31]/LDP[0:3]
LAD[0:31]/LDP[0:3]
Figure 39. Local Bus Signals, Non-Special Signals Only (PLL Enabled)
Output Signals:
show the local bus signals.
Input Signals:
Input Signal:
LSYNC_IN
LUPWAIT
LAD[0:31]
LGTA
LALE
t
t
LBKHOV1
LBKHOV2
t
LBKHOV3
t
LBKHOV4
NOTE
t
t
t
t
t
LBIVKH1
LBIVKH2
LBKHOX1
LBKHOX2
LBKHOX2
t
t
t
LBKHOZ1
LBKHOZ2
LBKHOZ2
t
LBOTOT
enhanced Local Bus Controller (eLBC)
t
t
LBIXKH1
LBIXKH2
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