HCTL-2017-PLC Avago Technologies US Inc., HCTL-2017-PLC Datasheet
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HCTL-2017-PLC
Specifications of HCTL-2017-PLC
HCTL-2017-PLC
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HCTL-2017-PLC Summary of contents
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... The HCTL-2021/2017 provides quadrature decoder output signals and cascade signals for use with many standard computer ICs. The HCTL-2021/2017 is compliant to RoHS directive and had been declared as a lead free product. Devices Part Number Description HCTL-2017 33 MHz clock operation ...
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... HCTL-2021 SHOWN 2 Soldering and Mounting Considerations 1 D0 VDD 20 2 CLK recommended to use manual soldering for HCTL- 2021/2017 launch pad devices due to the characteristics 3 SEL the material used in the launch pad design that not allow wave soldering Direct mounting on printed circuit board (PCB) only is ...
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Operating Characteristics Table 1. Absolute Maximum Ratings (All voltages below are referenced to VSS) Parameter DC Supply Voltage Input Voltage Storage Temperature Operating Temperature [1] Table 2. Recommended Operating Conditions Parameter Symbol DC Supply Voltage V Ambient Temperature [1] T ...
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... The proper signal U (high level (low level) will be CAS present before the rising edge of the CNT A pulse is presented on this LSTTL-compatible output when the HCTL-2021 internal counter overflows or underflows. The rising edge on this waveform may be used to trigger an external counter. These LSTTL-compatible tri-state outputs form an 8-bit output ports through which the contents of the 16-bit position latch may be read in 2 sequential bytes ...
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Switching Characteristics Table 5. Switching Characteristics Max/Min specifications at VDD = 5 -40 to +85 OC Symbol Description 1 t Clock Period CLK 2 t Pulse width, clock high CHH 3 t ...
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... Figure 4. Bus Control Timing Figure 5. Decoder, Cascade Output Timing Operation A block diagram of the HCTL-20xx family is shown in Figure 6. The operation of each major function is described in the following sections. Figure 6. Simplified Logic Diagram 6 ...
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Digital Noise Filter The digital noise filter section is responsible for rejecting noise on the incoming quadrature signals. The input section uses two techniques to implement improved noise rejection. Schmitt-trigger inputs and a three-clock- cycle delay filter combine to reject ...
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... IC before the count increments one-half of the maximum count capability. Two's-complement arithmetic is normally used to compute position from these periodic position updates. D. The system count is >16 bits so the HCTL-2021/2017 can be cascaded with other standard counter ICs to give absolute position. - low or high) has to be greater than E ) ...
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... Quadrature Decoder Output The quadrature decoder output section consists of count and up/down outputs derived from the 4x decoder mode of the HCTL-2021/2017. When the decoder has detected a count, a pulse, one-half clock cycle long, will be output on the CNT output will occur during the clock cycle in which the internal counter is updated ...
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... For example, suppose the HCTL-2021/2017 count is at FFFFh and an external counter is at F0h, with the count going up. A count occurring in the HCTL-2021/2017 will cause the counter to roll over and a cascade pulse will be generated. A read starting on this clock cycle will show FFFFh from the HCTL-2021/2017. The external ...
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... For proper operation of the inhibit logic during a two- byte read, OE and SEL must be synchronous with CLK due to the falling edge sampling of OE and SEL. The internal inhibit logic on the HCTL-2021/2017 inhibits the transfer of data from the counter to the position data latch during the time that the latch outputs are being read ...
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