MT46V64M16P-6T:A Micron Technology Inc, MT46V64M16P-6T:A Datasheet - Page 20
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MT46V64M16P-6T:A
Manufacturer Part Number
MT46V64M16P-6T:A
Description
DRAM Chip DDR SDRAM 1G-Bit 64Mx16 2.5V 66-Pin TSOP Tray
Manufacturer
Micron Technology Inc
Type
DDR SDRAMr
Datasheet
1.MT46V256M4P-6TA_TR.pdf
(82 pages)
Specifications of MT46V64M16P-6T:A
Density
1 Gb
Maximum Clock Rate
333 MHz
Package
66TSOP
Operating Supply Voltage
2.5 V
Maximum Random Access Time
0.7 ns
Operating Temperature
0 to 70 °C
Format - Memory
RAM
Memory Type
DDR SDRAM
Memory Size
1G (64M x 16)
Speed
6ns
Interface
Parallel
Voltage - Supply
2.3 V ~ 2.7 V
Package / Case
66-TSOP
Organization
64Mx16
Address Bus
16b
Access Time (max)
700ps
Operating Supply Voltage (typ)
2.5V
Package Type
TSOP
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Supply Current
275mA
Pin Count
66
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MT46V64M16P-6T:A
Manufacturer:
MICRON
Quantity:
5 530
Company:
Part Number:
MT46V64M16P-6T:A
Manufacturer:
MICRON
Quantity:
48
Part Number:
MT46V64M16P-6T:A
Manufacturer:
MICRON/美光
Quantity:
20 000
Table 15:
PDF: 09005aef80a2f898/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. I, Core DDR: Rev. B 12/07 EN
AC Characteristics
Parameter
Access window of DQ from CK/CK#
CK high-level width
Clock cycle time
CK low-level width
DQ and DM input hold time relative to DQS
DQ and DM input pulse width (for each input)
Access window of DQS from CK/CK#
DQS input high pulse width
DQS input low pulse width
DQS–DQ skew, DQS to last DQ valid, per group, per access
WRITE command to first DQS latching transition
DQ and DM input setup time relative to DQS
DQS falling edge from CK rising – hold time
DQS falling edge to CK rising – setup time
Half-clock period
Data-out High-Z window from CK/CK#
Address and control input hold time (slew rate ≥0.5 V/ns)
Address and control input pulse width (for each input)
Address and control input setup time (slew rate ≥0.5 V/ns)
Data-out Low-Z window from CK/CK#
LOAD MODE REGISTER command cycle time
DQ–DQS hold, DQS to first DQ to go non-valid, per access
Data hold skew factor
ACTIVE-to-READ with auto precharge command
ACTIVE-to-PRECHARGE command
ACTIVE-to-ACTIVE/AUTO REFRESH command period
ACTIVE-to-READ or WRITE delay
REFRESH-to-REFRESH command
interval
AUTO REFRESH command period
Average periodic refresh interval
PRECHARGE command period
DQS read preamble
DQS read postamble
ACTIVE bank a to ACTIVE bank b command
Terminating voltage delay to V
DQS write preamble
DQS write preamble setup time
DQS write postamble
Electrical Characteristics and Recommended AC Operating Conditions (-5B)
Notes 1–6, 16–18, 34 apply to the entire table; Notes appear on page 26;
0°C ≤ T
A
≤ +70°C; V
DD
DD
Q = +2.6V ±0.1V, V
CL = 3
CL = 2.5
CL = 2
1Gb
1Gb
1Gb
DD
= +2.6V ±0.1V
20
Symbol
t
t
t
CK (2.5)
t
t
t
DQSCK
t
t
t
t
t
WPRES
t
t
t
t
CK (3)
CK (2)
DQSQ
t
DQSH
t
WPRE
WPST
DIPW
DQSL
DQSS
t
t
t
t
t
t
t
t
t
t
MRD
REFC
RPRE
RPST
t
t
t
QHS
t
t
t
DSH
t
t
RAP
t
RCD
REFI
RRD
VTD
t
DSS
IPW
t
RAS
RFC
t
t
QH
AC
CH
DH
IH
DS
HP
HZ
RC
CL
IS
RP
LZ
Micron Technology, Inc., reserves the right to change products or specifications without notice.
F
F
Electrical Specifications – DC and AC
t
CH,
–0.70
–0.60
–0.70
t
t
Min
0.45
0.45
0.40
1.75
0.35
0.35
0.72
0.40
0.60
0.60
0.25
QHS
120
HP -
7.5
0.2
0.2
2.2
0.9
0.4
0.4
10
15
40
55
15
15
10
5
6
–
–
–
–
–
0
0
t
1Gb: x4, x8, x16 DDR SDRAM
CL
-5B
70,000
+0.70
+0.60
+0.70
Max
0.55
0.55
0.40
1.28
0.50
70.3
7.5
7.8
1.1
0.6
0.6
13
13
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
©2003 Micron Technology, Inc. All rights reserved.
Units
t
t
t
t
t
t
t
t
t
t
t
ns
CK
ns
ns
ns
CK
ns
ns
ns
CK
CK
ns
CK
ns
CK
CK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
µs
ns
CK
CK
ns
ns
CK
ns
CK
Notes
46, 52
26, 27
46, 52
27, 32
27, 32
19, 43
19, 43
26, 27
21, 22
52
32
35
15
15
36
24
50
24
31
31
44
44
20