MT48LC16M8A2TG-75:G Micron Technology Inc, MT48LC16M8A2TG-75:G Datasheet - Page 24

• Manufacturer Part Number: MT48LC16M8A2TG-75:G
• Description: DRAM Chip SDRAM 128M-Bit 16Mx8 3.3V 54-Pin TSOP-II Tray
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC16M8A2TG-75:G

• Package: 54TSOP-II
• Density: 128 Mb
• Address Bus Width: 14 Bit
• Operating Supply Voltage: 3.3 V
• Maximum Clock Rate: 133 MHz
• Maximum Random Access Time: 6|5.4 ns
• Operating Temperature: 0 to 70 °C

Operations
Bank/row Activation
PDF: 09005aef8091e66d/Source: 09005aef8091e625
128MSDRAM_2.fm - Rev. N 1/09 EN
The procedure for exiting self refresh requires a sequence of commands. First, CLK must
be stable (stable clock is defined as a signal cycling within timing constraints specified
for the clock pin) prior to CKE going back HIGH. After CKE is HIGH, the SDRAM must
have NOP commands issued (a minimum of 2 clocks) for
time is required for the completion of any internal refresh in progress.
Upon exiting the self refresh mode, AUTO REFRESH commands must be issued every
15.625µs or less because both SELF REFRESH and AUTO REFRESH utilize the row
refresh counter.
Self refresh is not supported on automotive temperature (AT) devices.
Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row
in that bank must be “opened.” This is accomplished via the ACTIVE command, which
selects both the bank and the row to be activated (see Figure 9 on page 25).
After opening a row (issuing an ACTIVE command), a READ or WRITE command may be
issued to that row, subject to the
the clock period and rounded up to the next whole number to determine the earliest
clock edge after the ACTIVE command on which a READ or WRITE command can be
entered. For example, a
results in 2.5 clocks, rounded to 3. This is reflected in Figure 10 on page 25, which covers
any case where 2 <
specification limits from time units to clock cycles.)
A subsequent ACTIVE command to a different row in the same bank can only be issued
after the previous active row has been “closed” (precharged). The minimum time
interval between successive ACTIVE commands to the same bank is defined by
A subsequent ACTIVE command to another bank can be issued while the first bank is
being accessed, which results in a reduction of total row-access overhead. The minimum
time interval between successive ACTIVE commands to different banks is defined by
t
RRD.
t
RCD (MIN)/
t
RCD specification of 20ns with a 125 MHz clock (8ns period)
24
t
t
CK ≤ 3. (The same procedure is used to convert other
RCD specification.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
RCD (MIN) should be divided by
128Mb: x4, x8, x16 SDRAM
t
XSR because this amount of
©1999 Micron Technology, Inc. All rights reserved.
Operations
t
RC.