MT48LC16M8A2TG-75:G Micron Technology Inc, MT48LC16M8A2TG-75:G Datasheet - Page 35
![no-image](/images/manufacturer_photos/0/4/441/micron_technology_inc_sml.jpg)
MT48LC16M8A2TG-75:G
Manufacturer Part Number
MT48LC16M8A2TG-75:G
Description
DRAM Chip SDRAM 128M-Bit 16Mx8 3.3V 54-Pin TSOP-II Tray
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet
1.MT48LC8M16A2P-75G_TR.pdf
(74 pages)
Specifications of MT48LC16M8A2TG-75:G
Package
54TSOP-II
Density
128 Mb
Address Bus Width
14 Bit
Operating Supply Voltage
3.3 V
Maximum Clock Rate
133 MHz
Maximum Random Access Time
6|5.4 ns
Operating Temperature
0 to 70 °C
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MT48LC16M8A2TG-75:G
Manufacturer:
MICRON
Quantity:
28
Figure 24:
Figure 25:
PDF: 09005aef8091e66d/Source: 09005aef8091e625
128MSDRAM_2.fm - Rev. N 1/09 EN
WRITE-to-PRECHARGE
Terminating a WRITE Burst
Notes:
Notes:
COMMAND
COMMAND
1. DQM could remain LOW in this example if the WRITE burst is a fixed length of two.
COMMAND
1. DQMs are LOW.
t WR @ t CLK ≥ 15ns
t WR = t CLK < 15ns
ADDRESS
ADDRESS
ADDRESS
DQM
DQM
CLK
DQ
DQ
CLK
TRANSITIONING DATA
DQ
BANK a,
BANK a,
WRITE
WRITE
BANK,
COL n
COL n
WRITE
COL n
D
D
T0
D
n
n
T0
IN
IN
n
IN
TERMINATE
n + 1
n + 1
BURST
NOP
NOP
T1
D
D
T1
IN
IN
t
WR
35
PRECHARGE
COMMAND
(ADDRESS)
(a or all)
DON’T CARE
BANK
(DATA)
T2
NOP
T2
NEXT
t
WR
TRANSITIONING DATA
PRECHARGE
(a or all)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
BANK
T3
NOP
t RP
NOP
NOP
T4
t RP
128Mb: x4, x8, x16 SDRAM
BANK a,
ACTIVE
ROW
NOP
T5
©1999 Micron Technology, Inc. All rights reserved.
DON’T CARE
BANK a,
ACTIVE
ROW
NOP
T6
Operations