XC2VP30-6FFG1152C Xilinx Inc, XC2VP30-6FFG1152C Datasheet - Page 118
![FPGA Virtex-II Pro™ Family 30816 Cells 1200MHz 0.13um/90nm (CMOS) Technology 1.5V 1152-Pin FCBGA](/photos/28/18/281832/xc2vp30-6ffg1152c__back__sml.jpg)
XC2VP30-6FFG1152C
Manufacturer Part Number
XC2VP30-6FFG1152C
Description
FPGA Virtex-II Pro™ Family 30816 Cells 1200MHz 0.13um/90nm (CMOS) Technology 1.5V 1152-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-II Pror
Datasheet
1.XC2VP20-5FGG676C.pdf
(430 pages)
Specifications of XC2VP30-6FFG1152C
Package
1152FCBGA
Family Name
Virtex-II ProÂ
Device Logic Units
30816
Number Of Registers
27392
Maximum Internal Frequency
1200 MHz
Typical Operating Supply Voltage
1.5 V
Maximum Number Of User I/os
644
Ram Bits
2506752
Number Of Logic Elements/cells
30816
Number Of Labs/clbs
3424
Total Ram Bits
2506752
Number Of I /o
644
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1364
Available stocks
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Quantity
Price
Company:
Part Number:
XC2VP30-6FFG1152C
Manufacturer:
XilinxInc
Quantity:
3 000
Company:
Part Number:
XC2VP30-6FFG1152C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC2VP30-6FFG1152C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
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Output Clock Jitter
Table 56: Output Clock Jitter
Output Clock Phase Alignment
Table 57: Output Clock Phase Alignment
DS083 (v4.7) November 5, 2007
Product Specification
Notes:
1. Use the Jitter Calculator on the Xilinx website (http://www.xilinx.com/applications/web_ds_v2/jitter_calc.htm) for CLKFX and
Notes:
1. “DLL outputs” is used here to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
2. CLKOUT_DUTY_CYCLE_DLL applies to the 1X clock outputs (CLK0, CLK90, CLK180, and CLK270) only if
3. Specification also applies to PSCLK.
Clock Synthesis Period Jitter
CLK0
CLK90
CLK180
CLK270
CLK2X, CLK2X180
CLKDV (integer division)
CLKDV (non-integer division)
CLKFX, CLKFX180
Phase Offset Between CLKIN and CLKFB
CLKIN/CLKFB
Phase Offset Between Any DCM Outputs
All CLK* outputs
Duty Cycle Precision
DLL outputs
CLKFX outputs
CLKFX180 output jitter.
DUTY_CYCLE_CORRECTION = TRUE.
Description
Description
(1)
R
CLKOUT_DUTY_CYCLE_DLL
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
CLKOUT_DUTY_CYCLE_FX
CLKIN_CLKFB_PHASE
CLKOUT_PHASE
CLKOUT_PER_JITT_DV1
CLKOUT_PER_JITT_DV2
CLKOUT_PER_JITT_180
CLKOUT_PER_JITT_270
CLKOUT_PER_JITT_2X
CLKOUT_PER_JITT_FX
CLKOUT_PER_JITT_90
CLKOUT_PER_JITT_0
Symbol
Symbol
www.xilinx.com
(2)
Constraints
Constraints
Note (1)
±140
±150
±100
±50
±100
±150
±150
±150
±200
±150
±300
–7
–7
Speed Grade
Speed Grade
Note (1)
±140
±150
±100
±100
±150
±150
±150
±200
±150
±300
±50
–6
–6
Note (1)
±140
±100
±150
±100
±150
±150
±150
±200
±150
±300
±50
–5
–5
Module 3 of 4
Units
Units
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
47
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