XC3S1500-4FG456I Xilinx Inc, XC3S1500-4FG456I Datasheet - Page 118
XC3S1500-4FG456I
Manufacturer Part Number
XC3S1500-4FG456I
Description
FPGA Spartan®-3 Family 1.5M Gates 29952 Cells 630MHz 90nm Technology 1.2V 456-Pin FBGA
Manufacturer
Xilinx Inc
Series
Spartan™-3r
Datasheet
1.XC3S50-4VQG100C.pdf
(217 pages)
Specifications of XC3S1500-4FG456I
Package
456FBGA
Family Name
Spartan®-3
Device Logic Units
29952
Device System Gates
1500000
Maximum Internal Frequency
630 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
333
Ram Bits
589824
Number Of Logic Elements/cells
29952
Number Of Labs/clbs
3328
Total Ram Bits
589824
Number Of I /o
333
Number Of Gates
1500000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
456-BBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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Manufacturer
Quantity
Price
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Spartan-3 FPGA Family: Pinout Descriptions
Table 79: Bitstream Options Affecting Spartan-3 Pins (Continued)
Setting Bitstream Generator Options
Refer to the
documentation.
118
M0
HSWAP_EN
TDI
TMS
TCK
TDO
Affected Pin
Name(s)
“BitGen” chapter
After configuration, this bitstream option either pulls M0 to
VCCAUX via a pull-up resistor, to ground via a pull-down resistor,
or allows M0 to float.
After configuration, this bitstream option either pulls HSWAP_EN
to VCCAUX via a pull-up resistor, to ground via a pull-down
resistor, or allows HSWAP_EN to float.
After configuration, this bitstream option either pulls TDI to
VCCAUX via a pull-up resistor, to ground via a pull-down resistor,
or allows TDI to float.
After configuration, this bitstream option either pulls TMS to
VCCAUX via a pull-up resistor, to ground via a pull-down resistor,
or allows TMS to float.
After configuration, this bitstream option either pulls TCK to
VCCAUX via a pull-up resistor, to ground via a pull-down resistor,
or allows TCK to float.
After configuration, this bitstream option either pulls TDO to
VCCAUX via a pull-up resistor, to ground via a pull-down resistor,
or allows TDO to float.
in the Xilinx ISE
Bitstream Generation Function
®
software
www.xilinx.com
DS099-4 (v2.5) December 4, 2009
HswapenPin •
Variable
TmsPin
Option
TdoPin
TckPin
M0Pin
TdiPin
Name
Product Specification
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
(default
Values
Pullup
Pulldown
Pullnone
Pullup
Pulldown
Pullnone
Pullup
Pulldown
Pullnone
Pullup
Pulldown
Pullnone
Pullup
Pulldown
Pullnone
Pullup
Pulldown
Pullnone
value)
R