889875AKLF IDT, Integrated Device Technology Inc, 889875AKLF Datasheet - Page 2

• Manufacturer Part Number: 889875AKLF
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Dividerr

Specifications of 889875AKLF

• Number Of Clock Inputs: 1
• Mode Of Operation: Differential
• Output Frequency: >2000MHz
• Output Logic Level: LVDS
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (typ): 2.5V
• Operating Supply Voltage (max): 2.625V
• Package Type: VFQFN
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Signal Type: CML/LVDS/LVPECL
• Mounting: Surface Mount
• Pin Count: 16
• Lead Free Status / RoHS Status: Compliant

Table 1. Pin Descriptions
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
IDT™ / ICS™ LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
Symbol
R
ICS889875
DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
PULLUP
5, 15, 16
Number
7, 14
1, 2
3, 4
10
11
12
13
6
8
9
Parameter
Input Pullup Resistor
S2, S1, S0
nDISABLE
nRESET/
Q0, nQ0
Q1, nQ1
V
Name
REF_AC
GND
V
nIN
V
nc
IN
DD
T
Unused
Output
Output
Output
Power
Power
Input
Input
Input
Input
Input
Type
Pullup
Pullup
Test Conditions
Description
Differential output pair. Divide by 1, 2, 4, 8, or 16. Unused outputs must be
terminated with 100
LVDS interface levels.
Differential output pair. Divide by 1, 2, 4, 8, or 16. Unused outputs must be
terminated with 100
LVDS interface levels.
Select pins. Internal 37k
Input threshold is V
No connect.
Power supply pins.
Synchronizing enable/disable pin. When LOW, resets the divider (divided by
1, 2, 4, 8 or 16 mode). When HIGH, disconnected. The reset and disable
function occurs on the next high-to-low clock input transition.
Input threshold is V
LVTTL / LVCMOS interface levels.
Inverting differential LVPECL clock input. R
Reference voltage for AC-coupled applications. Equal to V
(approx.). Maximum sink/source current is 0.5mA.
Termination center-tap input.
Non-inverting LVPECL differential clock input.
R
Power supply ground.
T
= 50
Ω
2
termination to V
DD
DD
Ω
Ω
/2. LVCMOS/LVTTL interface levels.
/2V. Includes a 37k
across the differential pair.
across the differential pair.
Ω
T
pullup resistor. Logic HIGH if left disconnected.
.
Minimum
ICS889875AK REV. B OCTOBER 27, 2008
Ω
T
Typical
pull-up resistor.
= 50
37
Ω
termination to V
Maximum
DD
– 1.4V
T
.
Units
k
Ω