ICS8737AGI-11T IDT, Integrated Device Technology Inc, ICS8737AGI-11T Datasheet - Page 8

• Manufacturer Part Number: ICS8737AGI-11T
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Dividerr

Specifications of ICS8737AGI-11T

• Number Of Clock Inputs: 2
• Mode Of Operation: Differential
• Output Frequency: 650MHz
• Output Logic Level: LVPECL
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Package Type: TSSOP
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 20
• Lead Free Status / RoHS Status: Not Compliant

R
I
CLK/nCLK I
For applications not requiring the use of the differential input,
both CLK and nCLK can be left floating. Though not required,
but for additional protection, a 1k
CLK to ground.
PCLK/nPCLK I
For applications not requiring the use of a differential input,
both the PCLK and nPCLK pins can be left floating. Though
not required, but for additional protection, a 1k
be tied from PCLK to ground.
LVCMOS C
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k
T
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
8737AGI-11
RTT =
NPUTS
ERMINATION FOR
ECOMMENDATIONS FOR
((V
:
FOUT
OH
F
IGURE
ONTROL
+ V
NPUT
OL
NPUT
:
) / (V
3A. LVPECL O
1
resistor can be used.
P
:
INS
LVPECL O
CC
:
Z
Z
– 2)) – 2
o
o
= 50
= 50
U
NUSED
Z
o
50
UTPUT
UTPUTS
resistor can be tied from
I
NPUT AND
T
ERMINATION
RTT
50
V
V
CC
CC
resistor can
FIN
- 2V
- 2V
O
D
UTPUT
IFFERENTIAL
www.idt.com
P
INS
8
50 transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion. Figures 3A and 3B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
O
LVPECL O
All unused LVPECL outputs can be left floating. We
recommend that there is no trace attached. Both sides of the
differential output pair should either be left floating or
terminated.
UTPUTS
-
FOUT
TO
F
- 3.3V LVPECL C
:
IGURE
UTPUT
3B. LVPECL O
Z
Z
o
o
= 50
= 50
125
84
UTPUT
ICS8737I-11
L
3.3V
OW
LOCK
T
125
84
ERMINATION
S
REV. C AUGUST 4, 2010
KEW
G
FIN
ENERATOR
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